Intel® desktop processors deliver superb computing power, performance, and reliability at home and at work. Our notebook processors let you work and play in places you never thought possible. Our server and workstation processors provide enhanced scalability, power, and performance for robust multi-processing environments. And our embedded and communications processors combine outstanding performance with scalable, power-efficient processing for a wide range of embedded applications.

Dell faces hurdles in luxury laptop push

Dell's ultra-sleek Adamo may be ill-timed and grasping for cachet that's not there.
Gizmodo summarized its review of the Adamo by saying: "Just don't dare buy this computer until Dell comes to their senses and realizes that $2,000+ is absurd for a 4-pound laptop with no graphics muscle."
Though I think Gizmodo misses the mark about "graphics muscle" (ultraportables are not designed or marketed as graphics powerhouses, or anything close to it), the reviewer is right about price--and high price implies cachet. Only Apple (and maybe the ThinkPad x301) can command the kind of cachet that demands $2,500 for a high-end laptop (i.e., the MacBook Air).

From top: Dell Mini Netbook, Apple MacBook Air, Dell Adamo
(Credit: iFixit / TechRepublic)
But there's a greater force conspiring against the Dell Adamo and even the Apple MBA: the Netbook.
High-end Netbooks, like the just-announced 11.6-inch Acer Aspire One, are priced well below $700, making it hard to plop down $2,700 for the 1.4GHz Adamo. Yes, the four-pound Dell is a stunning, superior design (0.65-inches thick, machined-aluminum chassis) with better hardware (Core 2 processor, 128GB solid-state drive standard, 13.4-inch 16:9 HD display with edge-to-edge glass) . But is it $2,000 better? In the age of the two-pound $500 "luxury" Netbook, definitely not.
And it's going to get worse. The Netbook's cousin-to-be, the cheap ultraportable, is going to make things even more uncomfortable for the Adamos of the world. A wave of $500-$900 ultrathin MacBook Air-like laptops are expected this summer. If these become popular, they will not only threaten the Adamo but possibly Netbooks too. (The Hewlett-Packard Pavilion dv2 is one of the first of many inexpensive ultraportables to come).
At the very least, this new category of laptops could push Netbooks down into the $100 to $300 price tier, instead of the typical $300 to $500 seen today.
Don't want a Netbook? Even "pricey" ultraportables can be had for under $1,300. A refurbished 1.8GHz MacBook Air with a solid-state drive is available today for $1,299 (not $1,099 as originally stated) direct from Apple (in my experience, many refurbished units are cosmetically new, but not without problems: see comments at bottom.)
Still want to fork over $2,700? Didn't think so.
(See: "Cracking Open the Dell Adamo" at TechRepublic.)
Note: the comment above about refurbished units revises the original text that said many refurbished units are "virtually new." This was stated too simplistically and did not accurately characterize the experience that I have had with refurbished laptops.

Server start-up taps IBM-Intel tech, eyes Web 2.0

A start-up founded by former Sun Microsystems computer scientists is tapping IBM and Intel hardware to accelerate the enormous server workloads of burgeoning Web 2.0 businesses.
Menlo Park, Calif.-based Schooner Information Technology announced Monday that it is readying a server appliance based on Intel's newest Nehalem processors and its solid-state drives. The first products are due by the end of May with volume shipments in the third quarter of 2009.
Hewlett-Packard and Fusion-io said recently that they are working on analogous technology and had achieved extremely high performance using Fusion-io's solid-state drives running on HP servers.
Schooner Information Technology's President and CEO John R. Busch was formerly research director of computer system architecture and analysis at Sun laboratories. Chairman and CTO Tom McWilliams was a lead engineer at Sun, working on server architecture and advanced CAD tools. Prior to that, McWilliams was a director in the MIPS division of Silicon Graphics. Both men were involved in moving Sun to multicore server architectures, according to Busch.
The company is funded by CMEA Capital and Redpoint Ventures. The current total investment is $15 million.
In a phone interview Monday, CEO Busch explained that the company has set out to fuse standalone high-performance server technologies into a faster organic whole. "Computer companies are pretty much selling boxes while others are selling networking. They're basically just selling component technologies," he said. "If you just speed up the processor or speed up the interconnect or add in flash drives, it will have a small effect."
"The observation I had when we started the company was that we really need to make a shift and we really need to put the middleware application and (our) new operating environment together with these technologies--tightly coupled with parallel flash memory and with Intel multicore processors. As opposed to loosely coupled, in order to bring their real inherent benefits through," Busch said.
Busch continued. "We pulled together a team of scientists and engineers and did the workload characterization and the modeling and the engineering and the optimization and we've been able to accomplish an eight times improvement in throughput performance," he said.
Michael Pray, vice president of sales and marketing, talked about specific challenges facing its customer base. "I would use the example of a social networker. When a person signs into their home page, there's a ton a data options that are returned back on those pages. The pain is around having to scale to meet the challenge. The more and more users you get, the more and more successful you are. You're kind of a victim of your own success with regards to the amount of data you need to serve up and continue the user response times," he said.
The company's core innovations, such as "extremely fast parallel thread switching between the (processor) cores," are, in essence, technologies to accelerate processing on the server computer.
The company uses IBM System x3650 M2 servers outfitted with Intel Nehalem processors and 512GB arrays of Intel solid-state drives. The products will be co-branded with IBM and will use IBM after-market support.
"We're big fans of (Intel) Nehalem multicore processors as well as their flash drives. We're in close cooperation both with their systems group with the processor as well as their NAND (flash) group," Pray said.

Intel issues solid-state drive fix

Intel said this addresses a problem first introduced by technology Web site PC Perspective in February. "This update implements several continuous improvements and optimizations to the drive algorithms including a resolution for a performance issue first reported by the PC Perspective," Intel said.
The PC Perspective review, titled "Long-term performance analysis of Intel Mainstream SSDs," claimed, among other things, that the Intel X25-M solid-state drive would degrade in performance as a result of "internal fragmentation."
"Keep in mind that the risk of a typical PC user experiencing this issue is very low," Intel said Monday. "We are offering this firmware download to our OEM customers and any consumers who have purchased the drives. Consumers with questions can contact their PC maker or visit Intel support for more information."
A Monday post by PC Perspective said that "the Intel guys were surprisingly down to earth and receptive to our input" and that Intel "replicated our findings in their lab. An added bonus was they...passed us a new firmware and were asking for our feedback."
Intel did not recognize the problem initially, saying in February: "Our labs currently have not been able to duplicate these results."

Intel profit down, but PC sales may be recovering

Intel's first-quarter profit fell about 56 percent from a year earlier, but Chief Executive Paul Otellini said PC sales were bottoming out.
Net income was $647 million, or 11 cents a share, down from $1.4 billion in the year-earlier period. Revenue was $7.1 billion, down about 27 percent from the $9.7 billion reported in the same period last year. Wall Street estimates were around 3 cents a share on revenue of $7 billion.
"We believe PC sales bottomed out during the first quarter and that the industry is returning to normal seasonal patterns," said Otellini, in a statement.
"I believe the worst is now behind us from an inventory correction and demand level adjustment perspective," Otellini said in prepared remarks during the company's earnings conference call Monday afternoon. He added that notebook inventory has now returned to normal levels.
"Everything I've seen suggests that the industry is at a new baseline," Otellini said, responding to an analyst's question during the conference call. "We're starting to see the normal (market) seasonality...and every sign we've seen in terms of markets recovering suggests that we're likely to see typical seasonality in the second half," he said.
Otellini also said in prepared remarks that the company had reduced inventory levels 19 percent below fourth-quarter levels and the number of employees had been reduced by 1,400 from the fourth quarter.
On the new product front, Otellini said that Intel's first 32-nanometer chip, Westmere, has been "pulled in" and will be shipping later this year.
The company said it is not providing a revenue outlook at this time.
"Due to continued economic uncertainty and limited visibility, Intel is not providing a revenue outlook at this time. For internal purposes, the company is currently planning for revenue approximately flat to the first quarter," Intel said.
Other Intel first-quarter 2009 earnings highlights:
Gross margin, a crucial indicator, was 45.6 percent, lower than the 53.1 percent in the fourth quarter.
Gross margin percentage in the second quarter is expected to be in the mid-40s.
Revenue from the Atom processor and chipsets was $219 million, down 27 percent sequentially.
Intel expects shipments of recently-introduced Nehalem processor to hit one million this month.
The average selling price for all microprocessors was approximately flat sequentially.
For full-year 2009, capital spending is expected to be slightly down from 2008.

IBM, Samsung, others team up on next-gen chips

IBM, Samsung Electronics, STMicroelectronics, and others are teaming up on the development of next-generation chip technology for small, low-power devices with one wary eye on Intel, which is expediting its move to chips with smaller geometries.
(Credit: IBM)
IBM and its semiconductor technology alliance partners are announcing the availability of 28-nanometer (nm) chip technology, a little more than a generation beyond the 45nm technologies currently used by Intel and Advanced Micro Devices in their latest chips.
The first products using chips based on this technology are expected in the second half of 2010, an IBM spokesman said. Devices will include smartphones and consumer electronics products.
The largest, single countervailing force to the IBM-led group is Intel. The Santa Clara, Calif.-based chip giant's chief executive, Paul Otellini, said Tuesday in a first-quarter earnings conference call that Intel is "pulling in" the release of "Westmere" chips based on 32nm technology and will ship silicon later this year.
Generally, the smaller the geometry, the faster and more power efficient the chip is.
The IBM alliance--which also includes the AMD manufacturing spin-off Globalfoundries, Chartered Semiconductor, and Infineon Technologies--are jointly developing the 28nm chipmaking process based on the partners' "high-k metal gate" (which minimizes current leakage), low-power complementary metal oxide semiconductor (CMOS) process technology.
The technology "can provide a 40 percent performance improvement and a more than 20 percent reduction in power, in a chip that is half the size, compared with 45nm technology," IBM said in a statement. "These improvements enable microchip designs with outstanding performance, smaller feature sizes and low standby power, contributing to faster processing speed and longer battery life in next-generation mobile Internet devices and other systems."
IBM said customers can begin their designs now using 32nm technology and then transition to 28nm for density and power advantages without the need for a major redesign.
One prominent customer is U.K.-based ARM, whose basic chip design has been used in billions of devices all over the world. ARM is collaborating with the IBM alliance to develop a design platform for 32nm and 28nm technology and is tuning its Cortex processor family and future processors to exploit the technology's capabilities, IBM said

One tale of woe: Apple, HP laptop 'refurbs'

Refurbished laptops from Apple and Hewlett-Packard are relatively inexpensive and, in many cases, virtually new. But it all depends on how you define "new."
Let me begin by saying that I would not recommend a refurbished laptop. That's just my experience, of course. I recognize that others have had positive experiences and that some would swear it's like buying a new computer, just cheaper. But I have purchased two refurbished laptops--one from Apple, another from HP--that were both defective out of the box.

"Refurbs" really a great deal?
Apple case first. I recently purchased a refurbished Apple MacBook Air. Unpacking it revealed a pristine, brand-new looking MBA. Until I turned it on. The screen was dimmer than the screen on a one-year-old Air I have been using and the backlighting was uneven. In short, the bottom 25 percent (roughly) of the screen was noticeably darker than other 75 percent of the screen.
Moreover, upon closer inspection I could see that the screen had rather prominent dark blotchy areas (more prominent than the "normal" blotching you get on these screens). Ironically, the much older Air did not exhibit this. Now, I realize that I may not have considered the screen defective if this had been my first Air and I hadn't been using another MBA (which, by the way, I had intended to pass on to someone else) that had a gorgeous, uniformly backlit screen. But nobody, I would submit, likes trading down from something great to something less than that.
And what is the single biggest difference (aside from specifications) between the two Airs? The non-defective, problem-free one was purchased new.
I have a lot of scary, unpleasant theories about refurbs--none of which could ever be proven unless I actually worked at a PC manufacturer--but I think I can safely say this much: some refurbs are less than meets the eye. They may look pristine on the outside but mask internal problems.
Which brings us to my HP business laptop refurb. This is a much longer story that I will summarize briefly as follows: out of the box, the keyboard was defective and the unit randomly shut down (that latter problem, I concluded, was due to overheating). I had to go through a pretty painstaking series of steps to get both of these problems resolved.
The moral of the story may be this: you get what you pay for. A buyer of a refurbished HP business laptop can save a lot of money--sometimes more than 50 percent off the list price of a new unit. The cost savings on a refurbished MacBook that is still being actively marketed by Apple is less: in the case of the Air, a few hundred dollars.
So, what is a refurbished laptop? Here's what HP says on its FAQ page:
"Stringent guidelines are followed. All units are brought up to fully functional condition, with defective parts replaced by working parts...Refurbished business products go through two quality control checks before being re-boxed for sale to ensure high reliability."
I'm sure both companies strive to offer just-like-new refurbished laptops but my experience is that refurbs may be more trouble than they're worth. I would like to hear the experiences readers have had.

Here come Intel's Westmere chips

Intel has been talking a lot about Westmere chips lately. So, here's a quick look at Intel's first chips based on 32-nanometer technology.
Chief Executive Paul Otellini addressed Westmere during the company's first-quarter earnings conference call this week, saying the Westmere chip design will ship later this year, earlier than expected. "We have shipped thousands of Westmere samples to over 30 customers already," Otellini said in the conference call.
Intel's current lineup is made up of processors based on 45-nanometer technology. Generally, the smaller the geometries, the faster and more power efficient the chip. The move to 32-nanometer will put Intel ahead of rival Advanced Micro Devices, which isn't expected to transition to 32-nanometer chips until late in 2010.
The first installment of the Westmere family, the Clarkdale and Arrandale processors, is expected later this year, according to published Intel documentation. Clarkdale is a 32-nanometer desktop processor with built-in graphics--what Intel describes as a "multi-chip package with graphics integrated in (the) processor." Arrandale is a version--also with integrated graphics--for the mobile market, due later this year.

Intel launches new chip logos, rating system

Intel has revamped its processor badging and rating system. Consumers are the main target, though business systems will get new badging too.
The new badges include a die (the chip minus the packaging) accent in the upper right hand corner, a prominent main brand (e.g., "Core"), and the modifier (e.g., "i7").
Intel has also instituted a star system that rates chips from five stars (best performance in class) to one star (lowest performance). "So when a consumer goes into a Best Buy store they can distinguish between Centrino, Core, Celeron, Core 2 Duo, Core 2 Quad," said Intel spokesman Bill Calder.
That may be a little easier said than done, however. Some consumers (but not including "tech savvy" Giampaolo, of course) will still need help from the sales person to decipher the badging. A daunting challenge in the case of consumer laptops, which are typically plastered with a hodgepodge of stickers from Intel, Nvidia, Advanced Micro Devices, AMD's ATI graphics chip unit, and other companies.
Intel is in the process of moving to a "pretty aggressive brand simplification plan," Calder said. "When we launched Core i7, we said we're moving to a single primary client brand, which is Core. We're moving in that direction," he said.
The Atom processor will not get a modifier. In the future, the Nehalem server processor, currently branded only as "Xeon" with a letter and number suffix, may also get new branding to make it more readily identifiable as part of the Nehalem architecture like its desktop sibling the Core i7, Calder said.

Intel adds new chips as Atom turns 1

Intel celebrated the first anniversary of the Atom processor by introducing two new models, while confirming the arrival of Nehalem-based mobile processors later this year and disclosing a new chip dubbed "Jasper Forest."
The chipmaker also did a live demonstration for the first time of the next-generation Atom-based platform, code-named Moorestown. The platform will include a new Moblin software version that will enable a PC-like Internet experience along with cellular voice capabilities, Intel said.

Intel senior vice president Anand Chandrasekher did a live demonstration of the upcoming Moorestown Atom chip in Beijing
(Credit: Intel)
Intel announced two new Atom processors for mobile Internet devices, or MIDs: the Z550 and Z515. The Z550 extends the performance of the Atom line to 2GHz. The Z515 incorporates the Intel Burst Performance Technology (Intel BPT), which enables the processor to run at 1.2GHz when performance is needed, Intel said.
Anand Chandrasekher, Intel senior vice president and general manager of the Ultra Mobility Group, in a keynote speech at the Intel Developer Forum in Beijing, discussed upcoming processors for laptops based on the Nehalem architecture that will be available in the second half of this year as part of the "Calpella" platform. These processors will be more powerful than their predecessors by including such technologies as Intel Hyper-Threading Technology and Intel Turbo Boost Technology.
Chandrasekher also touched on Intel's ultra low-voltage (ULV) processors and how they are creating a category of ultra-thin laptops less than 1-inch thick. Intel is slated to offer lower-priced versions of these processors by early summer that are expected to engender a class of low-cost ultra-thin laptops, which some have described as a MacBook Air for the masses.
Pat Gelsinger, Intel senior vice president and general manager of the Digital Enterprise Group, disclosed, for the first time, the Nehalem EP-based processor code-named Jasper Forest that is specifically designed for embedded and storage applications "to deliver optimal performance per watt...Jasper Forest will be offered in single-, dual- or quad-core designs; ranging from 23 watts to 85 watts," Intel said.

Intel® Celeron® Processor: Features and benefits

Intel® Wide Dynamic Execution Improves execution speed and efficiency, delivering more instructions per clock cycle. Each core can complete up to four full instructions simultaneously.
Intel® Smart Memory Access Improves system performance by optimizing the use of the available data bandwidth.
Intel® Advanced Digital Media Boost Accelerates the execution of Streaming SIMD Extension (SSE) instructions to significantly improve the performance on a broad range of applications, including video, audio, image, media boost, photo processing, multimedia, encryption, financial, engineering, and scientific applications. The 128-bit SSE instructions are now issued at a throughput rate of one per clock cycle, effectively doubling execution speed on a per clock basis over previous generation processors.
Intel® 64 architecture± An enhancement to Intel® 32-bit architecture that allows the processor to access larger amounts of memory. With appropriate 64-bit supporting hardware and software, platforms based on an Intel® processor supporting Intel® 64 architecture enable the use of extended virtual and physical memory.
Execute Disable Bit° Provides enhanced virus protection when deployed with a supported operating system. The Execute Disable Bit marks memory as executable or non-executable, allowing the processor to raise an error to the operating system. If malicious code attempts to run in non-executable memory, the malicious code is prevented from infecting the system.
For dual-core processing only:
Intel® Advanced Smart Cache The shared L2 cache is dynamically allocated to each processor core based on workload. This increases the probability that each core can access data from fast L2 cache, significantly reducing latency to frequently used data and improving performance.

Intel® Celeron® Processor

Overview: Intel® Celeron® processors provide a low-cost mobile computing solution for basic computing needs. Together with the Intel® 4 Series Express Chipsets and Intel® 965 Express Chipset, these Intel® Celeron® processors deliver exceptional value.

Intel® Celeron® Processor: Specifications

Processor Number L2 Cache Clock Speed Front Side Bus
T1700 1M 1.83 GHz 667 MHz
T1600 1M 1.66 GH 667 MHz
723 1M 1.2 GHz 800 MHz
585 1M 2.16 GHz 667 MHz
577 512K 2.00 GHz 667 MHz
570 512K 2.26 GHz 533 MHz
560 512K 2.13 GHz 533 MHz
550 1M 2.00 GHz 533 MHz
540 1M 1.86 GHz 533 MHz
530 1M 1.73 GHz 533 MHz
220 512K 1.20 GHz 533 MHz

Intel® Celeron® Processor

Datasheets: For Mobile Intel® 965 Express Chipset Family
This document covers the Intel® Celeron® processor 500 series for platforms based on Mobile Intel® 965 Express Chipset family. It is based on the new Intel® Core™ microarchitecture.
64-bit computing on Intel architecture requires a computer system with a processor, chipset, BIOS, operating system, device drivers and applications enabled for Intel® 64 architecture. Processors will not operate (including 32-bit operation) without an Intel® 64 Architecture-enabled BIOS. Performance will vary depending on your hardware and software configurations. Consult with your system vendor for more information.
Δ Intel® processor numbers are not a measure of performance. Processor numbers differentiate features within each processor family, not across different processor families.

Intel® Celeron® Processor 15

This generational and chronological list of Intel microprocessors attempts to present all of Intel's processors from the pioneering 4-bit 4004 (1971) to the present high-end offerings, the 64-bit Itanium 2 (2002) and Intel Core 2 and Xeon 5100 and 7100 series processors (2006). Concise technical data are given for each product.

Intel® Celeron® Processor 15

This generational and chronological list of Intel microprocessors attempts to present all of Intel's processors from the pioneering 4-bit 4004 (1971) to the present high-end offerings, the 64-bit Itanium 2 (2002) and Intel Core 2 and Xeon 5100 and 7100 series processors (2006). Concise technical data are given for each product.

Intel 4004: first single-chip microprocessor

Introduced November 15, 1971
Clock rate 740 kHz[1]
0.07 MIPS
Bus Width 4 bits (multiplexed address/data due to limited pins)
PMOS
Number of Transistors 2,300 at 10 µm
Addressable Memory 640 bytes
Program Memory 4 KB (4 KB)
One of the earliest Commercial Microprocessors (cf. Four Phase Systems AL1, F14 CADC)
Originally designed to be used in Busicom calculator

MCS-4 Family:

4004-CPU
4001-ROM & 4 Bit Port
4002-RAM & 4 Bit Port
4003-10 Bit Shift Register
4008-Memory+I/O Interface
4009-Memory+I/O Interface

4040

4040-CPU
4101-1024-bit (256 x 4) Static RAM with separate I/O
4201-4MHz Clock Generator
4207-General Purpose Byte I/O Port
4209-General Purpose Byte I/O Port
4211-General Purpose Byte I/O Port
4265-Programmable General Purpose I/O Device
4269-Programmable Keyboard Display Device
4289-Standard Memory Interface for MCS-4/40
4308-8192-bit (1024 x 8) ROM w/ 4-bit I/O Ports
4316-16384-bit (2048 x 8) Static ROM
4702-2048-bit (256 x 8) EPROM
4801-5.185 MHz Clock Generator Crystal for 4004/4201A or 4040/4201A

The 8-bit processors

8008

Introduced April 1, 1972
Clock rate 500 kHz (8008-1: 800 kHz)
0.05 MIPS
Bus Width 8 bits (multiplexed address/data due to limited pins)
Enhancement load PMOS logic
Number of Transistors 3,500 at 10 µm
Addressable memory 16 KB
Typical in dumb terminals, general calculators, bottling machines
Developed in tandem with 4004
Originally intended for use in the Datapoint 2200 terminal

8080

Introduced April 1, 1974
Clock rate 2 MHz
0.64 MIPS
Bus Width 8 bits data, 16 bits address
Enhancement load NMOS logic
Number of Transistors 6,000
Assembly language downwards compatible with 8008.
Addressable memory 64 KB
Up to 10X the performance of the 8008
Used in the Altair 8800, Traffic light controller, cruise missile
Required six support chips versus 20 for the 8008

8085

Introduced March 1976
Clock rate 5 MHz
0.37 MIPS
Bus Width 8 bits data, 16 bits address
Depletion load NMOS logic
Number of Transistors 6,500 at 3 µm
Binary compatible downwards with the 8080.
Used in Toledo scale. Also was used as a computer peripheral controller - modems, harddisks,printers, etc...
CMOS 80C85 in Mars Sojourner, Radio Shack Model 100 portable.
High level of integration, operating for the first time on a single 5 volt power supply, from 12 volts previously. Also featured serial I/O,3 maskable interrupts,1 Non-maskable interrupt,1 externally expandable interrupt w/[8259],status,DMA.

MCS-85 Family:

8085-CPU
8155-RAM+ 3 I/O Ports+Timer "Active Low CS"
8156-RAM+ 3 I/O Ports+Timer "Active High CS"
8185-SRAM
8202-Dynamic RAM Controller]
8203-Dynamic RAM Controller
8205-1 Of 8 Binary Decoder
8206-Error Detection & Correction Unit
8207-DRAM Controller
8210-TTL To MOS Shifter & High Voltage Clock Driver
8212-8 Bit I/O Port
8216-4 Bit Parallel Bidirectional Bus Driver
8219-Bus Controller
8222-Dynamic RAM Refresh Controller
8226-4 Bit Parallel Bidirectional Bus Driver
8231-Arithmetic Processing Unit
8232-Floating Point Processor
8237-DMA Controller
8251-Communication Controller
8253-Programmable Interval Timer
8254-Programmable Interval Timer
8255-Programmable Peripheral Interface
8256-Multifunction Support Controller
8257-DMA Controller
8259-Programmable Interrupt Controller
8271-Programmable Floppy Disk Controller
8272-Single/Double Density Floppy Disk Controller
8273-Programmable HDLC/SDLC Protocol Controller
8274-Multi-Protocol Serial Controller
8275-CRT Controller
8276-Small System CRT Controller
8278-Programmable KeyBoard Interface
8279-KeyBoard/Display Controller
8282-8-bit Non-Inverting Latch with Output Buffer
8283-8-bit Inverting Latch with Output Buffer
8291-GPIB Talker/Listener
8292-GPIB Controller
8293-GPIB Transceiver
8294-Data Encryption/Decryption Unit+1 O/P Port
8295-Dot Matrix Printer Controller
8296-GPIB Transceiver
8297-GPIB Transceiver
8355-16,384-bit (2048 x 8) ROM with I/O
8604-4096-bit (512 x 8) PROM
8702-2K-bit (256 x 8 ) PROM
8755-EPROM+2 I/O Ports

Intel 8048

MCS-48 Family
8020-Single-Component 8-Bit Microcontroller
8021-Single-Component 8-Bit Microcontroller
8022-Single-Component 8-Bit Microcontroller With On Chip A/D Converter
8031-Single-Component 8-Bit Microcontroller
8035-Single-Component 8-Bit Microcontroller
8039-Single-Component 8-Bit Microcontroller
8040-Single-Component 8-Bit Microcontroller
8041-Universal Peripheral Interface 8-Bit Slave Microcontroller
8641-Universal Peripheral Interface 8-Bit Slave Microcontroller
8741-Universal Peripheral Interface 8-Bit Slave Microcontroller
8042-Universal Peripheral Interface 8-Bit Slave Microcontroller
8242-Universal Peripheral Interface 8-Bit Slave Microcontroller
8742-Universal Peripheral Interface 8-Bit Slave Microcontroller
8243-Input/Output Expander
8044-High Performance 8-Bit Microcontroller With On-Chip Serial Communication Controller
8344-High Performance 8-Bit Microcontroller With On-Chip Serial Communication Controller
8744-High Performance 8-Bit Microcontroller With On-Chip Serial Communication Controller
8048-Single-Component 8-Bit Microcontroller
8748-Single-Component 8-Bit Microcontroller
8049-Single-Component 8-Bit Microcontroller
8749-Single-Component 8-Bit Microcontroller
8050-Single-Component 8-Bit Microcontroller

Single accumulator Harvard architecture

MCS-51 Family
8031-8-Bit Control-Oriented Microcontroller
8032-8-Bit Control-Oriented Microcontroller
8051-8-Bit Control-Oriented Microcontroller
8052-8-Bit Control-Oriented Microcontroller
8054-8-Bit Control-Oriented Microcontroller
8058-8-Bit Control-Oriented Microcontroller
8351-8-Bit Control-Oriented Microcontroller
8352-8-Bit Control-Oriented Microcontroller
8354-8-Bit Control-Oriented Microcontroller
8358-8-Bit Control-Oriented Microcontroller
8751-8-Bit Control-Oriented Microcontroller
8752-8-Bit Control-Oriented Microcontroller
8754-8-Bit Control-Oriented Microcontroller
8758-8-Bit Control-Oriented Microcontroller
80151-8-Bit Control-Oriented Microcontroller
83151-8-Bit Control-Oriented Microcontroller
87151-8-Bit Control-Oriented Microcontroller
80152-8-Bit Control-Oriented Microcontroller
83152-8-Bit Control-Oriented Microcontroller
80251-8-Bit Control-Oriented Microcontroller
83251-8-Bit Control-Oriented Microcontroller
87251-8-Bit Control-Oriented Microcontroller

MCS-96 Family

8094-16-Bit Microcontroller (48-Pin ROMLess Without A/D)
8095-16-Bit Microcontroller (48-Pin ROMLess With A/D)
8096-16-Bit Microcontroller (68-Pin ROMLess Without A/D)
8097-16-Bit Microcontroller (68-Pin ROMLess With A/D)
8394-16-Bit Microcontroller (48-Pin With ROM Without A/D)
8395-16-Bit Microcontroller (48-Pin With ROM With A/D)
8396-16-Bit Microcontroller (68-Pin With ROM Without A/D)
8397-16-Bit Microcontroller (68-Pin With ROM With A/D)
8794-16-Bit Microcontroller (48-Pin With EROM Without A/D)
8795-16-Bit Microcontroller (48-Pin With EROM With A/D)
8796-16-Bit Microcontroller (68-Pin With EROM Without A/D)
8797-16-Bit Microcontroller (68-Pin With EROM With A/D)
8098-16-Bit Microcontroller
8398-16-Bit Microcontroller
8798-16-Bit Microcontroller
83196-16-Bit Microcontroller
87196-16-Bit Microcontroller
80296-16-Bit Microcontroller

The bit-slice processor

3000 Family
Intel D3002.
Introduced 3rd Qtr, 1974 Members of the family
3001-Microcontrol Unit
3002-2-bit Arithmetic Logic Unit slice
3003-Look-ahead Carry Generator
3205-High-performance 6-bit Latch
3207-Quad Bipolar-to-MOS Level Shifter and Driver
3208-Hex Sense Amp and Latch for MOS Memories
3210-TTL-to-MOS Level Shifter and High Voltage Clock Driver
3211-ECL-to-MOS Level Shifter and High Voltage Clock Driver
3212-Multimode Latch Buffer
3214-Interrupt Control Unit
3216-Parallel,Inverting Bi-Directional Bus Driver
3222-Refresh Controller for 4K NMOS DRAMs
3226-Parallel,Inverting Bi-Directional Bus Driver
3232-Address Multiplexer and Refresh Counter for 4K DRAMs
3235-Quad Bipolar-to-MOS Driver
3242-Address Multiplexer and Refresh Counter for 16K DRAMs
3245-Quad Bipolar TTL-to-MOS Level Shifter and Driver for 4K
3246-Quad Bipolar ECL-to-MOS Level Shifter and Driver for 4K
3404-High-performance 6-bit Latch
3408-Hex Sense Amp and Latch for MOS Memories
Bus Width 2-n bits data/address (depending on number of slices used)

iPLDs:Intel Programmable Logic Devices

PLDs Family
iFX780-10ns FLEXlogic FPGA With SRAM Option
85C220-80 And 66 Fast Registerd bandwidth 8-Macrocell PLDs
85C224-80 And 66 Fast Registerd bandwidth 8-Macrocell PLDs
85C22V10-Fast 10-Macrocell CHMOS μPLD
85C060-Fast 16-Macrocell CHMOS PLD
85C090-Fast 24-Macrocell CHMOS PLD
85C508-Fast 1-Micron CHMOS Decoder/Latch μPLD
85C960-Programmable Bus Control PLD
5AC312-1-Micron CHMOS EPLD
5AC324-1-Micron CHMOS EPLD
5C121-EPLD
5C031-300 Gate CMOS PLD
5C032-8-Macrocell PLD
5C060-16-Macrocell PLD
5C090-24-Macrocell PLD
5C180-48-Macrocell PLD

Signal Processor

2910-PCM CODEC – µ LAW
2911-PCM CODEC – A LAW
2912-PCM Line Filters
2914-Combination Codec/Filter
2920-Signal Processor
2921-ROM Signal Processor
2951-CHMOS Advanced Telecommunication Controller
2952-Integrated I/O Controller
2970-Single Chip Modem

The 16-bit processors: origin of x86

Introduced June 8, 1978
Clock rates:
5 MHz with 0.33 MIPS
8 MHz with 0.66 MIPS
10 MHz with 0.75 MIPS
The memory is divided into odd and even banks. It accesses both the banks simultaneuosly in order to read 16 bit of data in one clock cycle.
Bus Width 16 bits data, 20 bits address
Number of Transistors 29,000 at 3 µm
Addressable memory 1 megabyte
Up to 10X the performance of 8080 (typically lower)
Used in portable computing, and in the IBM PS/2 Model 25 and Model 30. Also used in the AT&T PC6300 / Olivetti M24, a popular IBM PC-compatible (predating the IBM PS/2 line.)
Used segment registers to access more than 64 KB of data at once, which many programmers complained made their work excessively difficult.

Digital Clocks Processor

5000 Family
These devices are CMOS technology.
5101-1024-bit (256 x 4) Static RAM
5201/5202-LCD Decoder-Driver
5203 LCD Driver.
5204-Time Seconds/Date LCD Decoder-Driver
5234-Quad CMOS-to-MOS Level Shifter and Driver for 4K NMOS RAMs
5235-Quad CMOS TTL-to-MOS Level Shifter and Driver for 4K NMOS
5244-Quad CCD Clock Driver
5801-Low Power Oscillator-Divider
5810-Single Chip LCD Time/Seconds/Date Watch Circuit
5814 4-Digit LCD.
5816 6-Digit LCD.
5830 6-Digit LCD + Chronograph Business Sold.

80186

80186
Introduced 1982
Included two timers, a DMA controller, and an interrupt controller on the chip in addition to the processor (These were at fixed addresses which differed from the IBM PC, making it impossible to build a 100% PC-compatible computer around the 80186.)
Added a few opcodes and exceptions to the 8086 design; otherwise identical instruction set to 8086 and 8088.
Used mostly in embedded applications - controllers, point-of-sale systems, terminals, and the like
Used in several non-PC-Compatible MS-DOS computers including RM Nimbus, Tandy 2000
Later renamed the iAPX 186
[edit]
80188
A version of the 80186 with an 8-bit external data bus
Later renamed the iAPX 188
[edit]
80286
Introduced February 1, 1982
Clock rates:
6 MHz with 0.9 MIPS
8 MHz, 10 MHz with 1.5 MIPS
12.5 MHz with 2.66 MIPS
16 MHz, 20 MHz and 25 MHz available.
Bus Width 16 bits
Included memory protection hardware to support multitasking operating systems with per-process address space
Number of Transistors 134,000 at 1.5 µm
Addressable memory 16 MB (16 MB)
Added protected-mode features to 8086 with essentially the same instruction set
3-6X the performance of the 8086
Widely used in IBM-PC AT and AT clones contemporary to it
[edit]
32-bit processors: the non-x86 microprocessors
[edit]
iAPX 432
Introduced January 1, 1981 as Intel's first 32-bit microprocessor
Multi-chip CPU; Intel's first 32-bit microprocessor
Object/capability architecture
Microcoded operating system primitives
One terabyte virtual address space
Hardware support for fault tolerance
Two-chip General Data Processor (GDP), consists of 43201 and 43202
43203 Interface Processor (IP) interfaces to I/O subsystem
43204 Bus Interface Unit (BIU) simplifies building multiprocessor systems
43205 Memory Control Unit (MCU)
Architecture and execution unit internal data paths 32 bit
Clock rates:
5 MHz
7 MHz
8 MHz
[edit]
i960 aka 80960
Introduced April 5, 1988
RISC-like 32-bit architecture
Predominantly used in embedded systems
Evolved from the capability processor developed for the BiiN joint venture with Siemens
Many variants identified by two-letter suffixes.

80386SX (chronological entry)
Introduced June 16, 1988
See main entry

80376 (chronological entry)
Introduced January 16, 1989
See main entry
[edit]
i860 aka 80860
Introduced February 27, 1989
Intel's first superscalar processor
RISC 32/64-bit architecture, with pipeline characteristics very visible to programmer
Used in Intel Paragon massively parallel supercomputer
[edit]
XScale
Introduced August 23, 2000
32-bit RISC microprocessor based on the ARM architecture
Many variants, such as the PXA2xx applications processors, IOP3xx I/O processors and IXP2xxx and IXP4xx network processors.
[edit]
32-bit processors: the 80386 range
[edit]
80386DX
Introduced October 17, 1985
Clock rates:
16 MHz with 5 to 6 MIPS
20 MHz with 6 to 7 MIPS, introduced February 16, 1987
25 MHz with 8.5 MIPS, introduced April 4, 1988
33 MHz with 11.4 MIPS (9.4 SPECint92 on Compaq/i 16K L2), introduced April 10, 1989
Bus Width 32 bits
Number of Transistors 275,000 at 1 µm
Addressable memory 4 GB (4 GB)
Virtual memory 64 TB (64 TiB)
First x86 chip to handle 32-bit data sets
Reworked and expanded memory protection support including paged virtual memory and virtual-86 mode, features required by Windows 95 and OS/2 Warp
Used in Desktop computing

80960 (i960) (chronological entry)
Introduced April 5, 1988
See main entry
[edit]
80386SX
Introduced June 16, 1988
Clock rates:
16 MHz with 2.5 MIPS
20 MHz with 2.5 MIPS, 25 MHz with 2.7 MIPS, introduced January 25, 1989
33 MHz with 2.9 MIPS, introduced October 26, 1992
Internal architecture 32 bits
External data bus width 16 bits
External address bus width 24 bits
Number of Transistors 275,000 at 1 µm
Addressable memory 16 MB
Virtual memory 32 GB
Narrower buses enable low-cost 32-bit processing
Used in entry-level desktop and portable computing
No Math Co-Processor
[edit]
80376
Introduced January 16, 1989; Discontinued June 15, 2001
Variant of 386 intended for embedded systems
No "real mode", starts up directly in "protected mode"
Replaced by much more successful 80386EX from 1994

80860 (i860) (chronological entry)
Introduced February 27, 1989
See main entry

80486DX (chronological entry)
Introduced April 10, 1989
See main entry
[edit]
80386SL
Introduced October 15, 1990
Clock rates:
20 MHz with 4.21 MIPS
25 MHz with 5.3 MIPS, introduced September 30, 1991
Internal architecture 32 bits
External bus width 16 bits
Number of Transistors 855,000 at 1 µm
Addressable memory 4 GB
Virtual memory 1 TB
First chip specifically made for portable computers because of low power consumption of chip
Highly integrated, includes cache, bus, and memory controllers

80486SX/DX2/SL, Pentium, 80486DX4 (chronological entries)
Introduced 1991–1994
See main entries
[edit]
80386EX
Introduced August 1994
Variant of 80386SX intended for embedded systems
Static core, i.e. may run as slowly (and thus, power efficiently) as desired, down to full halt
On-chip peripherals:
Clock and power mgmt
Timers/counters
Watchdog timer
Serial I/O units (sync and async) and parallel I/O
DMA
RAM refresh
JTAG test logic
Significantly more successful than the 80376
Used aboard several orbiting satellites and microsatellites
Used in NASA's FlightLinux project
[edit]
32-bit processors: the 80486 range
[edit]
80486DX
Introduced April 10, 1989
Clock rates:
25 MHz with 20 MIPS (16.8 SPECint92, 7.40 SPECfp92)
33 MHz with 27 MIPS (22.4 SPECint92 on Micronics M4P 128 KB L2), introduced May 7, 1990
50 MHz with 41 MIPS (33.4 SPECint92, 14.5 SPECfp92 on Compaq/50L 256 KB L2), introduced June 24, 1991
Bus Width 32 bits
Number of Transistors 1.2 million at 1 µm; the 50 MHz was at 0.8 µm
Addressable memory 4 GB
Virtual memory 1 TB
Level 1 cache of 8 KB on chip
Math coprocessor on chip
50X performance of the 8088
Used in Desktop computing and servers
Family 4 model 3

80386SL (chronological entry)
Introduced October 15, 1990
See main entry
[edit]
80486SX
Introduced April 22, 1991
Clock rates:
16 MHz with 13 MIPS
20 MHz with 16.5 MIPS, introduced September 16, 1991
25 MHz with 20 MIPS (12 SPECint92), introduced September 16, 1991
33 MHz with 27 MIPS (15.86 SPECint92), introduced September 21, 1992
Bus Width 32 bits
Number of Transistors 1.185 million at 1 µm and 900,000 at 0.8 µm
Addressable memory 4 GB
Virtual memory 1 TB
Identical in design to 486DX but without math coprocessor. The first version was an 80486DX with disabled mathco in the chip and different pin configuration. If the user needed math co capabilities, he must add 487SX which was actually an 486DX with different pin configuration to prevent the user from installing a 486DX instead of 487SX, so with this configuration 486SX+487SX you had 2 identical CPU's with only 1 turned on)
Used in low-cost entry to 486 CPU desktop computing
Upgradable with the Intel OverDrive processor
Family 4 model 2
[edit]
80486DX2
Introduced March 3, 1992
Clock rates:
40 MHz
50 MHz
66 MHz
100 MHz (This was only made a short time due to high failure rates.)
[edit]
80486SL
Introduced November 9, 1992
Clock rates:
20 MHz with 15.4MIPS
25 MHz with 19 MIPS
33 MHz with 25 MIPS
Bus Width 32 bits
Number of Transistors 1.4 million at 0.8 µm
Addressable memory 4 GB
Virtual memory 1 TB
Used in notebook computers
Family 4 model 3

Pentium (chronological entry)
Introduced March 22, 1993
See main entry
[edit]
80486DX4
Introduced March 7, 1994
Clock rates:
75 MHz with 53 MIPS (41.3 SPECint92, 20.1 SPECfp92 on Micronics M4P 256 KB L2)
100 MHz with 70.7 MIPS (54.59 SPECint92, 26.91 SPECfp92 on Micronics M4P 256 KB L2)
Number of Transistors 1.6 million at 0.6 µm
Bus width 32 bits
Addressable memory 4 GB
Virtual memory 64 TB
Pin count 168 PGA Package, 208 sq ftP Package
Die size 345 mm²
Used in high performance entry-level desktops and value notebooks
Family 4 model 8

MCS-86 Family

8086-CPU
8087-Math-CoProcessor
8088-CPU
8089-Input/Output Co-Processor
8208-Dynamic RAM Controller
8284-Clock Generator & Driver
8286-Octal Bus Transceiver
8287-Octal Bus Transceiver
8288-Bus Controller
8289-Bus Arbiter

32-bit processors: the Pentium ("I")

Pentium ("Classic")
Bus width 64 bits
System bus clock rate 60 or 66 MHz
Address bus 32 bits
Addressable Memory 4 GB
Virtual Memory 64 TB
Superscalar architecture brought 5X the performance of the 33 MHz 486DX processor
Runs on 5 volts
Used in desktops
16 KB of L1 cache
P5 - 0.8 µm process technology
Introduced March 22, 1993
Number of transistors 3.1 million
Socket 4 273 pin PGA processor package
Package dimensions 2.16" x 2.16"
Family 5 model 1
Variants
60 MHz with 100 MIPS (70.4 SPECint92, 55.1 SPECfp92 on Xpress 256 KB L2)
66 MHz with 112 MIPS (77.9 SPECint92, 63.6 SPECfp92 on Xpress 256 KB L2)
P54 - 0.6 µm process technology
Socket 7 296/321 pin PGA package
Number of transistors 3.2 million
Variants
75 MHz Introduced October 10, 1994
90 MHz Introduced March 7, 1994
100 MHz Introduced March 7, 1994
120 MHz Introduced March 27, 1995
P54C - 0.35 µm process technology
Number of transistors 3.3 million
90 mm² die size
Family 5 model 2
Variants
120 MHz Introduced March, 1995
133 MHz Introduced June, 1995
150 MHz Introduced January 4, 1996
166 MHz Introduced January 4, 1996
200 MHz Introduced June 10, 1996

80486DX4 (chronological entry)
Introduced March 7, 1994
See main entry

80386EX (Intel386 EX) (chronological entry)
Introduced August 1994
See main entry

Pentium Pro (chronological entry)
Introduced November 1995
See main entry
[edit]
Pentium with MMX Technology
P55C - 0.35 µm process technology
Introduced January 8, 1997
Intel MMX instructions
Socket 7 296/321 pin PGA (pin grid array) package
32 KB L1 cache
Number of transistors 4.5 million
System bus clock rate 66 MHz
Basic P55C is family 5 model 4, mobile are family 5 model 7 and 8
Variants
166 MHz Introduced January 8, 1997
200 MHz Introduced January 8, 1997
233 MHz Introduced June 2, 1997
166 MHz (Mobile) Introduced January 12, 1998
200 MHz (Mobile) Introduced September 8, 1997
233 MHz (Mobile) Introduced September 8, 1997
266 MHz (Mobile) Introduced January 12, 1998
300 MHz (Mobile) Introduced January 7, 1999
[edit]
32-bit processors: P6/Pentium M microarchitecture
[edit]
Pentium Pro
Introduced November 1, 1995
Precursor to Pentium II and III
Primarily used in server systems
Socket 8 processor package (387 pins) (Dual SPGA)
Number of transistors 5.5 million
Family 6 model 1
0.6 µm process technology
16 KB L1 cache
256 KB integrated L2 cache
60 MHz system bus clock rate
Variants
150 MHz
0.35 µm process technology, or 0.35 µm CPU with 0.6 µm L2 cache
Number of transistors 5.5 million
512 KB or 256 KB integrated L2 cache
60 or 66 MHz system bus clock rate
Variants
166 MHz (66 MHz bus clock rate, 512 KB 0.35 µm cache) Introduced November 1, 1995
180 MHz (60 MHz bus clock rate, 256 KB 0.6 µm cache) Introduced November 1, 1995
200 MHz (66 MHz bus clock rate, 256 KB 0.6 µm cache) Introduced November 1, 1995
200 MHz (66 MHz bus clock rate, 512 KB 0.35 µm cache) Introduced November 1, 1995
200 MHz (66 MHz bus clock rate, 1 MB 0.35 µm cache) Introduced August 18, 1997

Pentium II

Introduced May 7, 1997
Pentium Pro with MMX and improved 16-bit performance
242-pin Slot 1 (SEC) processor package
Slot 1
Number of transistors 7.5 million
32 KB L1 cache
512 KB ½ bandwidth external L2 cache
The only Pentium II that did not have the L2 cache at ½ bandwidth of the core was the Pentium II 450 PE.
Klamath - 0.35 µm process technology (233, 266, 300 MHz)
66 MHz system bus clock rate
Family 6 model 3
Variants
233 MHz Introduced May 7, 1997
266 MHz Introduced May 7, 1997
300 MHz Introduced May 7, 1997
Deschutes - 0.25 µm process technology (333, 350, 400, 450 MHz)
Introduced January 26, 1998
66 MHz system bus clock rate (333 MHz variant), 100 MHz system bus clock rate for all models after
Family 6 model 5
Variants
333 MHz Introduced January 26, 1998
350 MHz Introduced April 15, 1998
400 MHz Introduced April 15, 1998
450 MHz Introduced August 24, 1998
233 MHz (Mobile) Introduced April 2, 1998
266 MHz (Mobile) Introduced April 2, 1998
333 MHz Pentium II Overdrive processor for Socket 8 Introduced August 10, 1998; Engineering Sample Photo
300 MHz (Mobile) Introduced September 9, 1998
333 MHz (Mobile)
[edit]
Celeron (Pentium II-based)
Covington - 0.25 µm process technology
Introduced April 15, 1998
242-pin Slot 1 SEPP (Single Edge Processor Package)
Number of transistors 7.5 million
66 MHz system bus clock rate
Slot 1
32 KB L1 cache
No L2 cache
Variants
266 MHz Introduced April 15, 1998
300 MHz Introduced June 9, 1998
Mendocino - 0.25 µm process technology
Introduced August 24, 1998
242-pin Slot 1 SEPP (Single Edge Processor Package), Socket 370 PPGA package
Number of transistors 19 million
66 MHz system bus clock rate
Slot 1, Socket 370
32 KB L1 cache
128 KB integrated cache
Family 6 model 6
Variants
300 A MHz Introduced August 24, 1998
333 MHz Introduced August 24, 1998
366 MHz Introduced January 4, 1999
400 MHz Introduced January 4, 1999
433 MHz Introduced March 22, 1999
466 MHz
500 MHz Introduced August 2, 1999
533 MHz Introduced January 4, 2000
266 MHz (Mobile)
300 MHz (Mobile)
333 MHz (Mobile) Introduced April 5, 1999
366 MHz (Mobile)
400 MHz (Mobile)
433 MHz (Mobile)
450 MHz (Mobile) Introduced February 14, 2000
466 MHz (Mobile)
500 MHz (Mobile) Introduced February 14, 2000

Pentium II Xeon (chronological entry)
Introduced June 29, 1998
See main entry

Pentium III

Katmai - 0.25 µm process technology
Introduced February 26, 1999
Improved PII, i.e. P6-based core, now including Streaming SIMD Extensions (SSE)
Number of transistors 9.5 million
512 KB ½ bandwidth L2 External cache
242-pin Slot 1 SECC2 (Single Edge Contact cartridge 2) processor package
System Bus clock rate 100 MHz, 133 MHz (B-models)
Slot 1
Family 6 model 7
Variants
450 MHz Introduced February 26, 1999
500 MHz Introduced February 26, 1999
550 MHz Introduced May 17, 1999
600 MHz Introduced August 2, 1999
533 MHz Introduced (133 MHz bus clock rate) September 27, 1999
600 MHz Introduced (133 MHz bus clock rate) September 27, 1999
Coppermine - 0.18 µm process technology
Introduced October 25, 1999
Number of transistors 28.1 million
256 KB Advanced Transfer L2 Cache (Integrated)
242-pin Slot-1 SECC2 (Single Edge Contact cartridge 2) processor package, 370-pin FC-PGA (Flip-chip pin grid array) package
System Bus clock rate 100 MHz (E-models), 133 MHz (EB models)
Slot 1, Socket 370
Family 6 model 8
Variants
500 MHz (100 MHz bus clock rate)
533 MHz
550 MHz (100 MHz bus clock rate)
600 MHz
600 MHz (100 MHz bus clock rate)
650 MHz (100 MHz bus clock rate) Introduced October 25, 1999
667 MHz Introduced October 25, 1999
700 MHz (100 MHz bus clock rate) Introduced October 25, 1999
733 MHz Introduced October 25, 1999
750 MHz (100 MHz bus clock rate) Introduced December 20, 1999
800 MHz (100 MHz bus clock rate) Introduced December 20, 1999
850 MHz (100 MHz bus clock rate) Introduced March 20, 2000
866 MHz Introduced March 20, 2000
933 MHz Introduced May 24, 2000
1000 MHz Introduced March 8, 2000 (Not widely available at time of release)
1100 MHz
1133 MHz (first version recalled, later re-released)
400 MHz (Mobile) Introduced October 25, 1999
450 MHz (Mobile) Introduced October 25, 1999
500 MHz (Mobile) Introduced October 25, 1999
600 MHz (Mobile) Introduced January 18, 2000
650 MHz (Mobile) Introduced January 18, 2000
700 MHz (Mobile) Introduced April 24, 2000
750 MHz (Mobile) Introduced June 19, 2000
800 MHz (Mobile) Introduced September 25, 2000
850 MHz (Mobile) Introduced September 25, 2000
900 MHz (Mobile) Introduced March 19, 2001
1000 MHz (Mobile) Introduced March 19, 2001
Tualatin - 0.13 µm process technology
Introduced July 2001
Number of transistors 28.1 million
32 KB L1 cache
256 KB or 512 KB Advanced Transfer L2 cache (Integrated)
370-pin FC-PGA2 (Flip-chip pin grid array) package
133 MHz system bus clock rate
Socket 370
Family 6 model 11
Variants
1133 MHz (256 KB L2)
1133 MHz (512 KB L2)
1200 MHz
1266 MHz (512 KB L2)
1333 MHz
1400 MHz (512 KB L2)
[edit]
Pentium II and III Xeon
PII Xeon
Variants
400 MHz Introduced June 29, 1998
450 MHz (512 KB L2 Cache) Introduced October 6, 1998
450 MHz (1 MB and 2 MB L2 Cache) Introduced January 5, 1999
PIII Xeon
Introduced October 25, 1999
Number of transistors: 9.5 million at 0.25 µm or 28 million at 0.18 µm)
L2 cache is 256 KB, 1 MB, or 2 MB Advanced Transfer Cache (Integrated)
Processor Package Style is Single Edge Contact Cartridge (S.E.C.C.2) or SC330
System Bus clock rate 133 MHz (256 KB L2 cache) or 100 MHz (1 - 2 MB L2 cache)
System Bus Width 64 bit
Addressable memory 64 GB
Used in two-way servers and workstations (256 KB L2) or 4- and 8-way servers (1 - 2 MB L2)
Family 6 model 10
Variants
500 MHz (0.25 µm process) Introduced March 17, 1999
550 MHz (0.25 µm process) Introduced August 23, 1999
600 MHz (0.18 µm process, 256 KB L2 cache) Introduced October 25, 1999
667 MHz (0.18 µm process, 256 KB L2 cache) Introduced October 25, 1999
733 MHz (0.18 µm process, 256 KB L2 cache) Introduced October 25, 1999
800 MHz (0.18 µm process, 256 KB L2 cache) Introduced January 12, 2000
866 MHz (0.18 µm process, 256 KB L2 cache) Introduced April 10, 2000
933 MHz (0.18 µm process, 256 KB L2 cache)
1000 MHz (0.18 µm process, 256 KB L2 cache) Introduced August 22, 2000
700 MHz (0.18 µm process, 1 - 2 MB L2 cache) Introduced May 22, 2000
[edit]
Celeron (Pentium III Coppermine-based)
Coppermine-128, 0.18 µm process technology
Introduced March, 2000
Streaming SIMD Extensions (SSE)
Socket 370, FC-PGA processor package
Number of transistors 28.1 million
66 MHz system bus clock rate, 100 MHz system bus clock rate from January 3, 2001
32 kB L1 cache
128 kB Advanced Transfer L2 cache
Family 6 model 8
Variants
533 MHz
566 MHz
600 MHz
633 MHz Introduced June 26, 2000
667 MHz Introduced June 26, 2000
700 MHz Introduced June 26, 2000
733 MHz Introduced November 13, 2000
766 MHz Introduced November 13, 2000
800 MHz Introduced January 3, 2001
850 MHz Introduced April 9, 2001
900 MHz Introduced July 2, 2001
950 MHz Introduced August 31, 2001
1000 MHz Introduced August 31, 2001
1100 MHz Introduced August 31, 2001
550 MHz (Mobile)
600 MHz (Mobile) Introduced June 19, 2000
650 MHz (Mobile) Introduced June 19, 2000
700 MHz (Mobile) Introduced September 25, 2000
750 MHz (Mobile) Introduced March 19, 2001
800 MHz (Mobile)
850 MHz (Mobile) Introduced July 2, 2001
600 MHz (LV Mobile)
500 MHz (ULV Mobile) Introduced January 30, 2001
600 MHz (ULV Mobile)

XScale (chronological entry)
Introduced August 23, 2000
See main entry

Pentium 4 (not 4EE, 4E, 4F), Itanium, P4-based Xeon, Itanium 2 (chronological entries)
Introduced April 2000 – July 2002
See main entries
[edit]
Celeron (Pentium III Tualatin-based)
Tualatin Celeron - 0.13 µm process technology
32 KB L1 cache
256 KB Advanced Transfer L2 cache
100 MHz system bus clock rate
Socket 370
Family 6 model 11
Variants
1.0 GHz
1.1 GHz
1.2 GHz
1.3 GHz
1.4 GHz
[edit]
Pentium M
Banias 0.13 µm process technology
Introduced March 2003
64 KB L1 cache
1 MB L2 cache (integrated)
Based on Pentium III core, with SSE2 SIMD instructions and deeper pipeline
Number of transistors 77 million
Micro-FCPGA, Micro-FCBGA processor package
Heart of the Intel mobile Centrino system
400 MHz Netburst-style system bus
Family 6 model 9
Variants
900 MHz (Ultra low voltage)
1.0 GHz (Ultra low voltage)
1.1 GHz (Low voltage)
1.2 GHz (Low voltage)
1.3 GHz
1.4 GHz
1.5 GHz
1.6 GHz
1.7 GHz
Dothan 0.09 µm (90 nm) process technology
Introduced May 2004
2 MB L2 cache
Revised data prefetch unit
400 MHz Netburst-style system bus
21W TDP
Variants
1.00 GHz (Pentium M 723) (Ultra low voltage, 5W TDP)
1.10 GHz (Pentium M 733) (Ultra low voltage, 5W TDP)
1.20 GHz (Pentium M 753) (Ultra low voltage, 5W TDP)
1.30 GHz (Pentium M 718) (Low voltage, 10W TDP)
1.40 GHz (Pentium M 738) (Low voltage, 10W TDP)
1.50 GHz (Pentium M 758) (Low voltage, 10W TDP)
1.60 GHz (Pentium M 778) (Low voltage, 10W TDP)
1.40 GHz (Pentium M 710)
1.50 GHz (Pentium M 715)
1.60 GHz (Pentium M 725)
1.70 GHz (Pentium M 735)
1.80 GHz (Pentium M 745)
2.00 GHz (Pentium M 755)
2.10 GHz (Pentium M 765)
Dothan 533 0.09 µm (90 nm) process technology
Introduced Q1 2005
Same as Dothan except with a 533 MHz NetBurst-style system bus and 27W TDP
Variants
1.60 GHz (Pentium M 730)
1.73 GHz (Pentium M 740)
1.86 GHz (Pentium M 750)
2.00 GHz (Pentium M 760)
2.13 GHz (Pentium M 770)
2.26 GHz (Pentium M 780)
Stealey 0.09 µm (90 nm) process technology
Introduced Q2 2007
512 KB L2, 3W TDP
Variants
600 MHz (A100)
800 MHz (A110)
[edit]
Celeron M
Banias-512 0.13 µm process technology
Introduced March 2003
64 KB L1 cache
512 KB L2 cache (integrated)
SSE2 SIMD instructions
No SpeedStep technology, is not part of the 'Centrino' package
Family 6 model 9
Variants
310 - 1.20 GHz
320 - 1.30 GHz
330 - 1.40 GHz
340 - 1.50 GHz
Dothan-1024 90 nm process technology
64 KB L1 cache
1 MB L2 cache (integrated)
SSE2 SIMD instructions
No SpeedStep technology, is not part of the 'Centrino' package
Variants
350 - 1.30 GHz
350J - 1.30 GHz, with Execute Disable bit
360 - 1.40 GHz
360J - 1.40 GHz, with Execute Disable bit
370 - 1.50 GHz, with Execute Disable bit
Family 6, Model 13, Stepping 8[2]
380 - 1.60 GHz, with Execute Disable bit
390 - 1.70 GHz, with Execute Disable bit
Yonah-1024 65 nm process technology
64 KB L1 cache
1 MB L2 cache (integrated)
SSE3 SIMD instructions, 533 MHz front-side bus, execute-disable bit
No SpeedStep technology, is not part of the 'Centrino' package
Variants
410 - 1.46 GHz
420 - 1.60 GHz,
423 - 1.06 GHz (ultra low voltage)
430 - 1.73 GHz
440 - 1.86 GHz
443 - 1.20 GHz (ultra low voltage)
450 - 2.00 GHz
[edit]
Intel Core
Yonah 0.065 µm (65 nm) process technology
Introduced January 2006
533/667 MHz front side bus
2 MB (Shared on Duo) L2 cache
SSE3 SIMD instructions
31W TDP (T versions)
Variants:
Intel Core Duo T2700 2.33 GHz
Intel Core Duo T2600 2.16 GHz
Intel Core Duo T2500 2 GHz
Intel Core Duo T2450 2 GHz
Intel Core Duo T2400 1.83 GHz
Intel Core Duo T2300 1.66 GHz
Intel Core Duo T2050 1.6 GHz
Intel Core Duo T2300e 1.66 GHz
Intel Core Duo T2080 1.73 GHz
Intel Core Duo L2500 1.83 GHz (Low voltage, 15W TDP)
Intel Core Duo L2400 1.66 GHz (Low voltage, 15W TDP)
Intel Core Duo L2300 1.5 GHz (Low voltage, 15W TDP)
Intel Core Duo U2500 1.2 GHz (Ultra low voltage, 9W TDP)
Intel Core Solo T1350 1.86 GHz (533 FSB)
Intel Core Solo T1300 1.66 GHz
Intel Core Solo T1200 1.5 GHz [3]
[edit]
Dual-Core Xeon LV
Sossaman 0.065 µm (65 nm) process technology
Introduced March 2006
Based on Yonah core, with SSE3 SIMD instructions
667 MHz frontside bus
2 MB Shared L2 cache
Variants
2.0 GHz
[edit]
32-bit processors: NetBurst microarchitecture
[edit]
Pentium 4
0.18 µm process technology (1.40 and 1.50 GHz)
Introduced November 20, 2000
L2 cache was 256 KB Advanced Transfer Cache (Integrated)
Processor Package Style was PGA423, PGA478
System Bus clock rate 400 MHz
SSE2 SIMD Extensions
Number of Transistors 42 million
Used in desktops and entry-level workstations
0.18 µm process technology (1.7 GHz)
Introduced April 23, 2001
See the 1.4 and 1.5 chips for details
0.18 µm process technology (1.6 and 1.8 GHz)
Introduced July 2, 2001
See 1.4 and 1.5 chips for details
Core Voltage is 1.15 volts in Maximum Performance Mode; 1.05 volts in Battery Optimized Mode
Power <1 watt in Battery Optimized Mode
Used in full-size and then light mobile PCs
0.18 µm process technology Willamette (1.9 and 2.0 GHz)
Introduced August 27, 2001
See 1.4 and 1.5 chips for details
Family 15 model 1
Pentium 4 (2 GHz, 2.20 GHz)
Introduced January 7, 2002
Pentium 4 (2.4 GHz)
Introduced April 2, 2002
0.13 µm process technology Northwood A (1.7, 1.8, 1.9, 2, 2.2, 2.4, 2.5, 2.6, 2.8(OEM),3.0(OEM) GHz)
Improved branch prediction and other microcodes tweaks
512 KB integrated L2 cache
Number of transistors 55 million
400 MHz system bus.
Family 15 model 2
0.13 µm process technology Northwood B (2.26, 2.4, 2.53, 2.66, 2.8, 3.06 GHz)
533 MHz system bus. (3.06 includes Intel's hyper threading technology).
0.13 µm process technology Northwood C (2.4, 2.6, 2.8, 3.0, 3.2, 3.4 GHz)
800 MHz system bus (all versions include Hyper Threading)
6500 to 10000 MIPS

Itanium (chronological entry)
Introduced 2001
See main entry
[edit]
Xeon
Official designation now Xeon, i.e. not "Pentium 4 Xeon"
Xeon 1.4, 1.5, 1.7 GHz
Introduced May 21, 2001
L2 cache was 256 KB Advanced Transfer Cache (Integrated)
Processor Package Style was Organic Land Grid Array 603 (OLGA 603)
System Bus clock rate 400 MHz
SSE2 SIMD Extensions
Used in high-performance and mid-range dual processor enabled workstations
Xeon 2.0 GHz and up to 3.6 GHz
Introduced September 25, 2001

Itanium 2 (chronological entry)
Introduced July 2002
See main entry

Mobile Pentium 4-M

Mobile Pentium 4-M
0.13 µm process technology
55 million transistors
cache L2 512 KB
BUS a 400 MHz
Supports up to 1 GB of DDR 266 MHz Memory
Supports ACPI 2.0 and APM 1.2 System Power Management
1.3 V - 1.2 V (SpeedStep)
Power: 1.2 GHz 20.8 W, 1.6 GHz 30 W, 2.6 GHz 35 W
Sleep Power 5 W (1.2 V)
Deeper Sleep Power = 2.9 W (1.0 V)
1.40 GHz - 23 April 2002
1.50 GHz - 23 April 2002
1.60 GHz - 4 March 2002
1.70 GHz - 4 March 2002
1.80 GHz - 23 April 2002
1.90 GHz - 24 June 2002
2.00 GHz - 24 June 2002
2.20 GHz - 16 September 2002
2.40 GHz - 14 January 2003
2.50 GHz - 16 April 2003
2.60 GHz - 11 June 2003
[edit]
Pentium 4 EE
Introduced September 2003
EE = "Extreme Edition"
Built from the Xeon's "Gallatin" core, but with 2 MB cache-
[edit]
Pentium 4E
Introduced February 2004
built on 0.09 µm (90 nm) process technology Prescott (2.4A, 2.8, 2.8A, 3.0, 3.2, 3.4, 3.6, 3.8) 1 MB L2 cache
533 MHz system bus (2.4A and 2.8A only)
Number of Transistors 125 million on 1 MB Models
Number of Transistors 169 million on 2 MB Models
800 MHz system bus (all other models)
Hyper-Threading support is only available on CPUs using the 800 MHz system bus.
The processor's integer instruction pipeline has been increased from 20 stages to 31 stages, which theoretically allows for even greater bandwidth.
7500 to 11000 MIPS
LGA-775 versions are in the 5xx series (32-bit) and 5x1 series (with Intel 64)
The 6xx series has 2 MB L2 cache and Intel 64
[edit]
Pentium 4F
Introduced Spring 2004
same core as 4E, "Prescott"
3.2–3.6 GHz
starting with the D0 stepping of this processor, Intel 64 64-bit extensions has also been incorporated
[edit]
64-bit processors: IA-64
New instruction set, not at all related to x86.
Before the feature was eliminated (Montecito, July 2006) IA-64 processors supported 32-bit x86 in hardware, but slowly.[dubious – discuss]
[edit]
Itanium
Code name Merced
Family 0x07
Released May 29, 2001
733 MHz and 800 MHz
2MB cache
all recalled and replaced by Itanium-II ?
[edit]
Itanium 2
Family 0x1F
Released July 2002
900 MHz - 1.6 GHz
McKinley 900MHz 1.5MB cache, Model 0x0
McKinley 1GHz, 3MB cache, Model 0x0
Deerfield 1GHz, 1.5MB cache, Model 0x1
Madison 1.3GHz, 3MB cache, Model 0x1
Madison 1.4GHz, 4MB cache, Model 0x1
Madison 1.5GHz, 6MB cache, Model 0x1
Madison 1.67GHz, 9MB cache, Model 0x1
Hondo 1.4GHz, 4MB cache, dual core MCM, Model 0x1

Pentium M (chronological entry)
Introduced March 2003
See main entry

Pentium 4EE, 4E (chronological entries)
Introduced September 2003, February 2004, respectively
See main entries
[edit]
64-bit processors: Intel 64 - NetBurst
Intel Extended Memory 64 Technology
Mostly compatible with AMD's AMD64 architecture
Introduced Spring 2004, with the Pentium 4F (D0 and later P4 steppings)
[edit]
Pentium 4F
Prescott-2M built on 0.09 µm (90 nm) process technology
2.8-3.8 GHz (model numbers 6x0)
Introduced February 20, 2005
Same features as Prescott with the addition of:-
2 MB cache
Intel 64bit
Enhanced Intel SpeedStep Technology (EIST)
Cedar Mill built on 0.065 µm (65 nm) process technology
3.0-3.6 (model numbers 6x1)
Introduced January 16, 2006
die shrink of Prescott-2M
Same features as Prescott-2M
[edit]
Pentium D
Main article: List of Intel Pentium D microprocessors
Dual-core microprocessor
No Hyper-Threading
800(4x200) MHz front side bus
Smithfield - 90 nm process technology (2.66–3.2 GHz)
Introduced May 26, 2005
2.66–3.2 GHz (model numbers 805-840)
Number of Transistors 230 million
1 MB x 2 (non-shared, 2 MB total) L2 cache
Cache coherency between cores requires communication over the FSB
Performance increase of 60% over similarly clocked Prescott
2.66 GHz (533 MHz FSB) Pentium D 805 introduced December 2005
Contains 2x Prescott dies in one package
Presler - 65 nm process technology (2.8–3.6 GHz)
Introduced January 16, 2006
2.8–3.6 GHz (model numbers 915-960)
Number of Transistors 376 million
2 MB x 2 (non-shared, 4 MB total) L2 cache
Contains 2x Cedar Mill dies in one package
[edit]
Pentium Extreme Edition
Dual-core microprocessor
Enabled Hyper-Threading
800(4x200) MHz front side bus
]
Smithfield - 90 nm process technology (3.2 GHz)
Variants
Pentium 840 EE - 3.20 GHz (2 x 1 MB L2)
Presler - 65 nm process technology (3.46, 3.73)
2 MB x 2 (non-shared, 4 MB total) L2 cache
Variants
Pentium 955 EE - 3.46 GHz, 1066 MHz front side bus
Pentium 965 EE - 3.73 GHz, 1066 MHz front side bus
[edit]
Xeon
Nocona
Introduced 2004
Irwindale
Introduced 2004
Cranford
Introduced April 2005
MP version of Nocona
Potomac
Introduced April 2005
Cranford with 8 MB of L3 cache
Paxville DP (2.8 GHz)
Introduced October 10, 2005
Dual-core version of Irwindale, with 4 MB of L2 Cache (2 MB per core)
2.8 GHz
800 MT/s front side bus
Paxville MP - 90 nm process (2.67 - 3.0 GHz)
Introduced November 1, 2005
Dual-Core Xeon 7000 series
MP-capable version of Paxville DP
2 MB of L2 Cache (1 MB per core) or 4 MB of L2 (2 MB per core)
667 MT/s FSB or 800 MT/s FSB
Dempsey - 65 nm process (2.67 - 3.73 GHz)
Introduced May 23, 2006
Dual-Core Xeon 5000 series
MP version of Presler
667 MT/s or 1066 MT/s FSB
4 MB of L2 Cache (2 MB per core)
Socket J, also known as LGA 771.
Tulsa - 65 nm process (2.5 - 3.4 GHz)
Introduced August 29, 2006
Dual-Core Xeon 7100-series
Improved version of Paxville MP
667 MT/s or 800 MT/s FSB
[edit]
64-bit processors: Intel 64 - Core microarchitecture
[edit]
Xeon
Woodcrest - 65 nm process technology
Server and Workstation CPU (SMP support for dual CPU system)
Introduced June 26, 2006
Dual-Core
Intel VT, multiple OS support
EIST (Enhanced Intel SpeedStep Technology) in 5140, 5148LV, 5150, 5160
Execute Disable Bit
TXT, enhanced security hardware extensions
SSSE3 SIMD instructions
iAMT2 (Intel Active Management Technology), remotely manage computers
Variants
Xeon 5160 - 3.00 GHz (4 MB L2, 1333 MHz FSB, 80 W)
Xeon 5150 - 2.66 GHz (4 MB L2, 1333 MHz FSB, 65 W)
Xeon 5140 - 2.33 GHz (4 MB L2, 1333 MHz FSB, 65 W)
Xeon 5130 - 2.00 GHz (4 MB L2, 1333 MHz FSB, 65 W)
Xeon 5120 - 1.86 GHz (4 MB L2, 1066 MHz FSB, 65 W)
Xeon 5110 - 1.60 GHz (4 MB L2, 1066 MHz FSB, 65 W)
Xeon 5148LV - 2.33 GHz (4 MB L2, 1333 MHz FSB, 40 W) -- Low Voltage Edition
Clovertown - 65 nm process technology
Server and Workstation CPU (SMP support for dual CPU system)
Introduced Dec 13th 2006
Quad Core
Intel VT, multiple OS support
EIST (Enhanced Intel SpeedStep Technology) in E5365, L5335
Execute Disable Bit
TXT, enhanced security hardware extensions
SSSE3 SIMD instructions
iAMT2 (Intel Active Management Technology), remotely manage computers
Variants
Xeon X5355 - 2.66 GHz (2x4 MB L2, 1333 MHz FSB, 105 W)
Xeon E5345 - 2.33 GHz (2x4 MB L2, 1333 MHz FSB, 80 W)
Xeon E5335 - 2.00 GHz (2x4 MB L2, 1333 MHz FSB, 80 W)
Xeon E5320 - 1.86 GHz (2x4 MB L2, 1066 MHz FSB, 65 W)
Xeon E5310 - 1.60 GHz (2x4 MB L2, 1066 MHz FSB, 65 W)
Xeon L5320 - 1.86 GHz (2x4 MB L2, 1066 MHz FSB, 50 W)-- Low Voltage Edition
[edit]
Intel Core 2
Conroe - 65 nm process technology
Desktop CPU (SMP support restricted to 2 CPUs)
Two cores on one die
Introduced July 27, 2006
SSSE3 SIMD instructions
Number of Transistors 291 Million
64 KB of L1 cache per core (32+32 KB 8-way)
Intel VT, multiple OS support
TXT, enhanced security hardware extensions
Execute Disable Bit
EIST (Enhanced Intel SpeedStep Technology)
iAMT2 (Intel Active Management Technology), remotely manage computers
LGA775
Variants
Core 2 Duo E6850 - 3.00 GHz (4 MB L2, 1333 MHz FSB)
Core 2 Duo X6800 - 2.93 GHz (4 MB L2, 1066 MHz FSB)
Core 2 Duo E6750 - 2.67 GHz (4 MB L2, 1333 MHz FSB)
Core 2 Duo E6700 - 2.67 GHz (4 MB L2, 1066 MHz FSB)
Core 2 Duo E6600 - 2.40 GHz (4 MB L2, 1066 MHz FSB)
Core 2 Duo E6550 - 2.33 GHz (4 MB L2, 1333 MHz FSB)
Core 2 Duo E6420 - 2.13 GHz (4 MB L2, 1066 MHz FSB)
Core 2 Duo E6400 - 2.13 GHz (2 MB L2, 1066 MHz FSB)
Core 2 Duo E6320 - 1.86 GHz (4 MB L2, 1066 MHz FSB)
Core 2 Duo E6300 - 1.86 GHz (2 MB L2, 1066 MHz FSB)
Conroe XE - 65 nm process technology
Desktop Extreme Edition CPU (SMP support restricted to 2 CPUs)
Introduced July 27, 2006
same features as Conroe
LGA775
Variants
Core 2 Extreme X6800 - 2.93 GHz (4 MB L2, 1066 MHz FSB)
Allendale - 65 nm process technology
Desktop CPU (SMP support restricted to 2 CPUs)
Two CPUs on one die
Introduced January 21, 2007
SSSE3 SIMD instructions
Number of Transistors 167 Million
TXT, enhanced security hardware extensions
Execute Disable Bit
EIST (Enhanced Intel SpeedStep Technology)
iAMT2 (Intel Active Management Technology), remotely manage computers
LGA775
Variants
Core 2 Duo E4600 - 2.40 GHz (2 MB L2, 800 MHz FSB)
Core 2 Duo E4500 - 2.20 GHz (2 MB L2, 800 MHz FSB)
Core 2 Duo E4400 - 2.00 GHz (2 MB L2, 800 MHz FSB)
Core 2 Duo E4300 - 1.80 GHz (2 MB L2, 800 MHz FSB)
Merom - 65 nm process technology
Mobile CPU (SMP support restricted to 2 CPUs)
Introduced July 27, 2006
Family 6, Model 15, Stepping 10
same features as Conroe
Socket M / Socket P
Variants
Core 2 Duo T7800 - 2.60 GHz (4 MB L2, 800 MHz FSB) (Santa Rosa platform)
Core 2 Duo T7700 - 2.40 GHz (4 MB L2, 800 MHz FSB)
Core 2 Duo T7600 - 2.33 GHz (4 MB L2, 667 MHz FSB)
Core 2 Duo T7500 - 2.20 GHz (4 MB L2, 800 MHz FSB)
Core 2 Duo T7400 - 2.16 GHz (4 MB L2, 667 MHz FSB)
Core 2 Duo T7300 - 2.00 GHz (4 MB L2, 800 MHz FSB)
Core 2 Duo T7250 - 2.00 GHz (2 MB L2, 800 MHz FSB)
Core 2 Duo T7200 - 2.00 GHz (4 MB L2, 667 MHz FSB)
Core 2 Duo T7100 - 1.80 GHz (2 MB L2, 800 MHz FSB)
Core 2 Duo T5600 - 1.83 GHz (2 MB L2, 667 MHz FSB)
Core 2 Duo T5550 - 1.83 GHz (2 MB L2, 667 MHz FSB, no VT)
Core 2 Duo T5500 - 1.66 GHz (2 MB L2, 667 MHz FSB, no VT)
Core 2 Duo T5470 - 1.60 GHz (2 MB L2, 800 MHz FSB, no VT)
Core 2 Duo T5450 - 1.66 GHz (2 MB L2, 667 MHz FSB, no VT)
Core 2 Duo T5300 - 1.73 GHz (2 MB L2, 533 MHz FSB, no VT)
Core 2 Duo T5270 - 1.40 GHz (2 MB L2, 800 MHz FSB, no VT)
Core 2 Duo T5250 - 1.50 GHz (2 MB L2, 667 MHz FSB, no VT)
Core 2 Duo T5200 - 1.60 GHz (2 MB L2, 533 MHz FSB, no VT)
Core 2 Duo L7500 - 1.60 GHz (4 MB L2, 800 MHz FSB) (Low Voltage)
Core 2 Duo L7400 - 1.50 GHz (4 MB L2, 667 MHz FSB) (Low Voltage)
Core 2 Duo L7300 - 1.40 GHz (4 MB L2, 800 MHz FSB) (Low Voltage)
Core 2 Duo L7200 - 1.33 GHz (4 MB L2, 667 MHz FSB) (Low Voltage)
Core 2 Duo U7700 - 1.33 GHz (2 MB L2, 533 MHz FSB) (Ultra Low Voltage)
Core 2 Duo U7600 - 1.20 GHz (2 MB L2, 533 MHz FSB) (Ultra Low Voltage)
Core 2 Duo U7500 - 1.06 GHz (2 MB L2, 533 MHz FSB) (Ultra Low Voltage)
Kentsfield - 65 nm process technology
Two dual-core cpu dies in one package.
Desktop CPU Quad Core (SMP support restricted to 4 CPUs)
Introduced December 13, 2006
same features as Conroe but with 4 CPU Cores
Number of Transistors 586 Million
Socket 775
Family 6, Model 15, Stepping 11
Variants
Core 2 Extreme QX6850 - 3 GHz (2x4 MB L2 Cache, 1333 MHz FSB)
Core 2 Extreme QX6800 - 2.93 GHz (2x4 MB L2 Cache, 1066 MHz FSB) (Apr 9th 07)
Core 2 Extreme QX6700 - 2.66 GHz (2x4 MB L2 Cache, 1066 MHz FSB) (Nov 14th 06)
Core 2 Quad Q6700 - 2.66 GHz (2x4 MB L2 Cache, 1066 MHz FSB) (Jul 22nd 07)
Core 2 Quad Q6600 - 2.40 GHz (2x4 MB L2 Cache, 1066 MHz FSB) (Jan 7th 07)
Wolfdale - 45 nm process technology
Die shrink of Conroe
Same features as Conroe with the addition of:-
50% more cache, 6 MB as opposed to 4 MB
Intel Trusted Execution Technology
SSE4 SIMD instructions
Number of Transistors 410 Million
Variants
Core 2 Duo E8600 - 3.33 GHz (6 MB L2, 1333 MHz FSB)
Core 2 Duo E8500 - 3.16 GHz (6 MB L2, 1333 MHz FSB)
Core 2 Duo E8400 - 3.00 GHz (6 MB L2, 1333 MHz FSB)
Core 2 Duo E8300 - 2.83 GHz (6 MB L2, 1333 MHz FSB)
Core 2 Duo E8200 - 2.66 GHz (6 MB L2, 1333 MHz FSB)
Core 2 Duo E8190 - 2.66 GHz (6 MB L2, 1333 MHz FSB, no TXT, no VT)
Yorkfield - 45 nm process technology
Quad core CPU
Die shrink of Kentsfield
Contains 2x Wolfdale dual core dies in one package
Same features as Wolfdale
Number of Transistors 820 Million
Variants
Core 2 Extreme QX9770 - 3.2 GHz (2x6 MB L2, 1600 MHz FSB)
Core 2 Extreme QX9650 - 3 GHz (2x6 MB L2, 1333 MHz FSB)
Core 2 Quad Q9650 - 3 GHz (2x6 MB L2, 1333 MHz FSB)
Core 2 Quad Q9550 - 2.83 GHz (2x6 MB L2, 1333 MHz FSB, 95W TDP)
Core 2 Quad Q9550s - 2.83 GHz (2x6 MB L2, 1333 MHz FSB, 65W TDP)
Core 2 Quad Q9450 - 2.66 GHz (2x6 MB L2, 1333 MHz FSB, 95W TDP)
Core 2 Quad Q9400 - 2.66 GHz (2x3 MB L2, 1333 MHz FSB, 95W TDP)
Core 2 Quad Q9400s - 2.66 GHz (2x3 MB L2, 1333 MHz FSB, 65W TDP)
Core 2 Quad Q9300 - 2.5 GHz (2x3 MB L2, 1333 MHz FSB, 95W TDP)
Core 2 Quad Q8300 - 2.5 GHz (2x2 MB L2, 1333 MHz FSB, 95W TDP)
Core 2 Quad Q8200 - 2.33 GHz (2x2 MB L2, 1333 MHz FSB, 95W TDP)
Core 2 Quad Q8200s - 2.33 GHz (2x2 MB L2, 1333 MHz FSB, 65W TDP)
[edit]
Pentium Dual Core
Allendale - 65 nm process technology
Desktop CPU (SMP support restricted to 2 CPUs)
Two CPUs on one die
Introduced January 21, 2007
SSSE3 SIMD instructions
Number of Transistors 167 Million
TXT, enhanced security hardware extensions
Execute Disable Bit
EIST (Enhanced Intel SpeedStep Technology)
Variants
Intel Pentium E2220 - 2.40 GHz (1 MB L2, 800 MHz FSB)
Intel Pentium E2200 - 2.20 GHz (1 MB L2, 800 MHz FSB)
Intel Pentium E2180 - 2.00 GHz (1 MB L2, 800 MHz FSB)
Intel Pentium E2160 - 1.80 GHz (1 MB L2, 800 MHz FSB)
Intel Pentium E2140 - 1.60 GHz (1 MB L2, 800 MHz FSB)
Wolfdale 45 nm process technology
Intel Pentium E5400 - 2.70 GHz (2MB L2,800 MHz FSB)
Intel Pentium E5300 - 2.60 GHz (2MB L2,800 MHz FSB)
Intel Pentium E5200 - 2.50 GHz (2MB L2,800 MHz FSB)
[edit]
Celeron M
Merom-1024 65 nm process technology
64 KB L1 cache
1 MB L2 cache (integrated)
SSE3 SIMD instructions, 533 MHz front-side bus, execute-disable bit, 64-bit
No SpeedStep technology, is not part of the 'Centrino' package
Variants
520 - 1.60 GHz
530 - 1.73 GHz
540 - 1.86 GHz
550 - 2.00 GHz
[edit]
Core i7
Bloomfield - 45 nm process technology
256 KB L2 cache
8 MB L3 cache
front side bus replaced with QuickPath up to 6.4GT/s
Hyper-Threading is again included. This had previously been removed at the introduction of Core line
781 million transistors
introduced November 17, 2008
Variants
920 - 2.66 GHz
940 - 2.93 GHz
965 (extreme edition) - 3.20 GHz
[edit]
Intel 805xx product codes
Intel discontinued the use of part numbers such as 80486 in the marketing of mainstream x86-architecture microprocessors with the introduction of the Pentium brand in 1993. However, numerical codes, in the 805xx range, continued to be assigned to these processors for internal and part numbering uses. The following is a list of such product codes in numerical order:

Intel CEO: big future for 'CULV' laptops

Intel Chief Executive Paul Otellini said low-cost, ultrathin laptops with future Intel processors will be a big trend, a development that could upset the Netbook cart.

HP Pavilion dv2: harbinger of things to come
(Credit: CNET Reviews)
During Intel's first-quarter earnings conference call Monday afternoon, Otellini had a surprising amount to say about Intel's upcoming consumer ultra-low-voltage (CULV) processors, designed to fit into future ultrathin laptops that are expected to be priced significantly below $1,700-and-up luxury laptops such as the Apple MacBook Air and the recently-introduced Dell Adamo. The category of upcoming CULV-based laptops has been described by some observers as the MacBook Air for the masses.
CULV chips will be based on mainstream Intel chip designs, such as Intel's Core architecture, differentiating them from the lower-performance Atom processor, which powers low-cost Netbooks.
Otellini said in prepared remarks during the conference call that Intel "looks forward to the launch of our consumer ultra-low-voltage products, which will enable many new sleek thin-and-light notebooks at very compelling price points."
And later in the conference call, responding to an analyst's question, he said: "The big trend in notebooks this year, starting mid-year, is likely to be very well designed thin-and-light notebooks using the CULV or ultra-low-voltage products."
Otellini continued. "And I think you'll see those at very attractive price points. Up to this point in time, those machines have been sort of executive jewelry and I think they'll hit mainstream consumer price points."
He said that these notebooks will be different from Netbooks. "And we're expecting (there will be) a more clear distinguishing set of characteristics between Netbooks and notebooks," he said.
One issue likely to emerge is, why would anyone buy a $500 Netbook, like the HP Mini-Note 2140, if these more powerful, sleek laptops are available?
The Intel CEO also said that new versions of the Atom processor are coming and mentioned a dual-core version. Intel currently offers a dual-core 330 Atom model for Nettops--a low-cost desktop PC category--so this would presumably be in addition to this sole dual-core Atom offering.
Otellinli also said that the future Larrabee graphics processor shown at the Intel Developers Conference in Beijing last week was a "high-end version" and added that "there's obviously other versions that have far fewer cores for different price points. What you saw is the 'extreme' version, let me put it that way." Volume shipments of Larrabee are expected early next year, he said.