Pentium III

Katmai - 0.25 µm process technology
Introduced February 26, 1999
Improved PII, i.e. P6-based core, now including Streaming SIMD Extensions (SSE)
Number of transistors 9.5 million
512 KB ½ bandwidth L2 External cache
242-pin Slot 1 SECC2 (Single Edge Contact cartridge 2) processor package
System Bus clock rate 100 MHz, 133 MHz (B-models)
Slot 1
Family 6 model 7
Variants
450 MHz Introduced February 26, 1999
500 MHz Introduced February 26, 1999
550 MHz Introduced May 17, 1999
600 MHz Introduced August 2, 1999
533 MHz Introduced (133 MHz bus clock rate) September 27, 1999
600 MHz Introduced (133 MHz bus clock rate) September 27, 1999
Coppermine - 0.18 µm process technology
Introduced October 25, 1999
Number of transistors 28.1 million
256 KB Advanced Transfer L2 Cache (Integrated)
242-pin Slot-1 SECC2 (Single Edge Contact cartridge 2) processor package, 370-pin FC-PGA (Flip-chip pin grid array) package
System Bus clock rate 100 MHz (E-models), 133 MHz (EB models)
Slot 1, Socket 370
Family 6 model 8
Variants
500 MHz (100 MHz bus clock rate)
533 MHz
550 MHz (100 MHz bus clock rate)
600 MHz
600 MHz (100 MHz bus clock rate)
650 MHz (100 MHz bus clock rate) Introduced October 25, 1999
667 MHz Introduced October 25, 1999
700 MHz (100 MHz bus clock rate) Introduced October 25, 1999
733 MHz Introduced October 25, 1999
750 MHz (100 MHz bus clock rate) Introduced December 20, 1999
800 MHz (100 MHz bus clock rate) Introduced December 20, 1999
850 MHz (100 MHz bus clock rate) Introduced March 20, 2000
866 MHz Introduced March 20, 2000
933 MHz Introduced May 24, 2000
1000 MHz Introduced March 8, 2000 (Not widely available at time of release)
1100 MHz
1133 MHz (first version recalled, later re-released)
400 MHz (Mobile) Introduced October 25, 1999
450 MHz (Mobile) Introduced October 25, 1999
500 MHz (Mobile) Introduced October 25, 1999
600 MHz (Mobile) Introduced January 18, 2000
650 MHz (Mobile) Introduced January 18, 2000
700 MHz (Mobile) Introduced April 24, 2000
750 MHz (Mobile) Introduced June 19, 2000
800 MHz (Mobile) Introduced September 25, 2000
850 MHz (Mobile) Introduced September 25, 2000
900 MHz (Mobile) Introduced March 19, 2001
1000 MHz (Mobile) Introduced March 19, 2001
Tualatin - 0.13 µm process technology
Introduced July 2001
Number of transistors 28.1 million
32 KB L1 cache
256 KB or 512 KB Advanced Transfer L2 cache (Integrated)
370-pin FC-PGA2 (Flip-chip pin grid array) package
133 MHz system bus clock rate
Socket 370
Family 6 model 11
Variants
1133 MHz (256 KB L2)
1133 MHz (512 KB L2)
1200 MHz
1266 MHz (512 KB L2)
1333 MHz
1400 MHz (512 KB L2)
[edit]
Pentium II and III Xeon
PII Xeon
Variants
400 MHz Introduced June 29, 1998
450 MHz (512 KB L2 Cache) Introduced October 6, 1998
450 MHz (1 MB and 2 MB L2 Cache) Introduced January 5, 1999
PIII Xeon
Introduced October 25, 1999
Number of transistors: 9.5 million at 0.25 µm or 28 million at 0.18 µm)
L2 cache is 256 KB, 1 MB, or 2 MB Advanced Transfer Cache (Integrated)
Processor Package Style is Single Edge Contact Cartridge (S.E.C.C.2) or SC330
System Bus clock rate 133 MHz (256 KB L2 cache) or 100 MHz (1 - 2 MB L2 cache)
System Bus Width 64 bit
Addressable memory 64 GB
Used in two-way servers and workstations (256 KB L2) or 4- and 8-way servers (1 - 2 MB L2)
Family 6 model 10
Variants
500 MHz (0.25 µm process) Introduced March 17, 1999
550 MHz (0.25 µm process) Introduced August 23, 1999
600 MHz (0.18 µm process, 256 KB L2 cache) Introduced October 25, 1999
667 MHz (0.18 µm process, 256 KB L2 cache) Introduced October 25, 1999
733 MHz (0.18 µm process, 256 KB L2 cache) Introduced October 25, 1999
800 MHz (0.18 µm process, 256 KB L2 cache) Introduced January 12, 2000
866 MHz (0.18 µm process, 256 KB L2 cache) Introduced April 10, 2000
933 MHz (0.18 µm process, 256 KB L2 cache)
1000 MHz (0.18 µm process, 256 KB L2 cache) Introduced August 22, 2000
700 MHz (0.18 µm process, 1 - 2 MB L2 cache) Introduced May 22, 2000
[edit]
Celeron (Pentium III Coppermine-based)
Coppermine-128, 0.18 µm process technology
Introduced March, 2000
Streaming SIMD Extensions (SSE)
Socket 370, FC-PGA processor package
Number of transistors 28.1 million
66 MHz system bus clock rate, 100 MHz system bus clock rate from January 3, 2001
32 kB L1 cache
128 kB Advanced Transfer L2 cache
Family 6 model 8
Variants
533 MHz
566 MHz
600 MHz
633 MHz Introduced June 26, 2000
667 MHz Introduced June 26, 2000
700 MHz Introduced June 26, 2000
733 MHz Introduced November 13, 2000
766 MHz Introduced November 13, 2000
800 MHz Introduced January 3, 2001
850 MHz Introduced April 9, 2001
900 MHz Introduced July 2, 2001
950 MHz Introduced August 31, 2001
1000 MHz Introduced August 31, 2001
1100 MHz Introduced August 31, 2001
550 MHz (Mobile)
600 MHz (Mobile) Introduced June 19, 2000
650 MHz (Mobile) Introduced June 19, 2000
700 MHz (Mobile) Introduced September 25, 2000
750 MHz (Mobile) Introduced March 19, 2001
800 MHz (Mobile)
850 MHz (Mobile) Introduced July 2, 2001
600 MHz (LV Mobile)
500 MHz (ULV Mobile) Introduced January 30, 2001
600 MHz (ULV Mobile)

XScale (chronological entry)
Introduced August 23, 2000
See main entry

Pentium 4 (not 4EE, 4E, 4F), Itanium, P4-based Xeon, Itanium 2 (chronological entries)
Introduced April 2000 – July 2002
See main entries
[edit]
Celeron (Pentium III Tualatin-based)
Tualatin Celeron - 0.13 µm process technology
32 KB L1 cache
256 KB Advanced Transfer L2 cache
100 MHz system bus clock rate
Socket 370
Family 6 model 11
Variants
1.0 GHz
1.1 GHz
1.2 GHz
1.3 GHz
1.4 GHz
[edit]
Pentium M
Banias 0.13 µm process technology
Introduced March 2003
64 KB L1 cache
1 MB L2 cache (integrated)
Based on Pentium III core, with SSE2 SIMD instructions and deeper pipeline
Number of transistors 77 million
Micro-FCPGA, Micro-FCBGA processor package
Heart of the Intel mobile Centrino system
400 MHz Netburst-style system bus
Family 6 model 9
Variants
900 MHz (Ultra low voltage)
1.0 GHz (Ultra low voltage)
1.1 GHz (Low voltage)
1.2 GHz (Low voltage)
1.3 GHz
1.4 GHz
1.5 GHz
1.6 GHz
1.7 GHz
Dothan 0.09 µm (90 nm) process technology
Introduced May 2004
2 MB L2 cache
Revised data prefetch unit
400 MHz Netburst-style system bus
21W TDP
Variants
1.00 GHz (Pentium M 723) (Ultra low voltage, 5W TDP)
1.10 GHz (Pentium M 733) (Ultra low voltage, 5W TDP)
1.20 GHz (Pentium M 753) (Ultra low voltage, 5W TDP)
1.30 GHz (Pentium M 718) (Low voltage, 10W TDP)
1.40 GHz (Pentium M 738) (Low voltage, 10W TDP)
1.50 GHz (Pentium M 758) (Low voltage, 10W TDP)
1.60 GHz (Pentium M 778) (Low voltage, 10W TDP)
1.40 GHz (Pentium M 710)
1.50 GHz (Pentium M 715)
1.60 GHz (Pentium M 725)
1.70 GHz (Pentium M 735)
1.80 GHz (Pentium M 745)
2.00 GHz (Pentium M 755)
2.10 GHz (Pentium M 765)
Dothan 533 0.09 µm (90 nm) process technology
Introduced Q1 2005
Same as Dothan except with a 533 MHz NetBurst-style system bus and 27W TDP
Variants
1.60 GHz (Pentium M 730)
1.73 GHz (Pentium M 740)
1.86 GHz (Pentium M 750)
2.00 GHz (Pentium M 760)
2.13 GHz (Pentium M 770)
2.26 GHz (Pentium M 780)
Stealey 0.09 µm (90 nm) process technology
Introduced Q2 2007
512 KB L2, 3W TDP
Variants
600 MHz (A100)
800 MHz (A110)
[edit]
Celeron M
Banias-512 0.13 µm process technology
Introduced March 2003
64 KB L1 cache
512 KB L2 cache (integrated)
SSE2 SIMD instructions
No SpeedStep technology, is not part of the 'Centrino' package
Family 6 model 9
Variants
310 - 1.20 GHz
320 - 1.30 GHz
330 - 1.40 GHz
340 - 1.50 GHz
Dothan-1024 90 nm process technology
64 KB L1 cache
1 MB L2 cache (integrated)
SSE2 SIMD instructions
No SpeedStep technology, is not part of the 'Centrino' package
Variants
350 - 1.30 GHz
350J - 1.30 GHz, with Execute Disable bit
360 - 1.40 GHz
360J - 1.40 GHz, with Execute Disable bit
370 - 1.50 GHz, with Execute Disable bit
Family 6, Model 13, Stepping 8[2]
380 - 1.60 GHz, with Execute Disable bit
390 - 1.70 GHz, with Execute Disable bit
Yonah-1024 65 nm process technology
64 KB L1 cache
1 MB L2 cache (integrated)
SSE3 SIMD instructions, 533 MHz front-side bus, execute-disable bit
No SpeedStep technology, is not part of the 'Centrino' package
Variants
410 - 1.46 GHz
420 - 1.60 GHz,
423 - 1.06 GHz (ultra low voltage)
430 - 1.73 GHz
440 - 1.86 GHz
443 - 1.20 GHz (ultra low voltage)
450 - 2.00 GHz
[edit]
Intel Core
Yonah 0.065 µm (65 nm) process technology
Introduced January 2006
533/667 MHz front side bus
2 MB (Shared on Duo) L2 cache
SSE3 SIMD instructions
31W TDP (T versions)
Variants:
Intel Core Duo T2700 2.33 GHz
Intel Core Duo T2600 2.16 GHz
Intel Core Duo T2500 2 GHz
Intel Core Duo T2450 2 GHz
Intel Core Duo T2400 1.83 GHz
Intel Core Duo T2300 1.66 GHz
Intel Core Duo T2050 1.6 GHz
Intel Core Duo T2300e 1.66 GHz
Intel Core Duo T2080 1.73 GHz
Intel Core Duo L2500 1.83 GHz (Low voltage, 15W TDP)
Intel Core Duo L2400 1.66 GHz (Low voltage, 15W TDP)
Intel Core Duo L2300 1.5 GHz (Low voltage, 15W TDP)
Intel Core Duo U2500 1.2 GHz (Ultra low voltage, 9W TDP)
Intel Core Solo T1350 1.86 GHz (533 FSB)
Intel Core Solo T1300 1.66 GHz
Intel Core Solo T1200 1.5 GHz [3]
[edit]
Dual-Core Xeon LV
Sossaman 0.065 µm (65 nm) process technology
Introduced March 2006
Based on Yonah core, with SSE3 SIMD instructions
667 MHz frontside bus
2 MB Shared L2 cache
Variants
2.0 GHz
[edit]
32-bit processors: NetBurst microarchitecture
[edit]
Pentium 4
0.18 µm process technology (1.40 and 1.50 GHz)
Introduced November 20, 2000
L2 cache was 256 KB Advanced Transfer Cache (Integrated)
Processor Package Style was PGA423, PGA478
System Bus clock rate 400 MHz
SSE2 SIMD Extensions
Number of Transistors 42 million
Used in desktops and entry-level workstations
0.18 µm process technology (1.7 GHz)
Introduced April 23, 2001
See the 1.4 and 1.5 chips for details
0.18 µm process technology (1.6 and 1.8 GHz)
Introduced July 2, 2001
See 1.4 and 1.5 chips for details
Core Voltage is 1.15 volts in Maximum Performance Mode; 1.05 volts in Battery Optimized Mode
Power <1 watt in Battery Optimized Mode
Used in full-size and then light mobile PCs
0.18 µm process technology Willamette (1.9 and 2.0 GHz)
Introduced August 27, 2001
See 1.4 and 1.5 chips for details
Family 15 model 1
Pentium 4 (2 GHz, 2.20 GHz)
Introduced January 7, 2002
Pentium 4 (2.4 GHz)
Introduced April 2, 2002
0.13 µm process technology Northwood A (1.7, 1.8, 1.9, 2, 2.2, 2.4, 2.5, 2.6, 2.8(OEM),3.0(OEM) GHz)
Improved branch prediction and other microcodes tweaks
512 KB integrated L2 cache
Number of transistors 55 million
400 MHz system bus.
Family 15 model 2
0.13 µm process technology Northwood B (2.26, 2.4, 2.53, 2.66, 2.8, 3.06 GHz)
533 MHz system bus. (3.06 includes Intel's hyper threading technology).
0.13 µm process technology Northwood C (2.4, 2.6, 2.8, 3.0, 3.2, 3.4 GHz)
800 MHz system bus (all versions include Hyper Threading)
6500 to 10000 MIPS

Itanium (chronological entry)
Introduced 2001
See main entry
[edit]
Xeon
Official designation now Xeon, i.e. not "Pentium 4 Xeon"
Xeon 1.4, 1.5, 1.7 GHz
Introduced May 21, 2001
L2 cache was 256 KB Advanced Transfer Cache (Integrated)
Processor Package Style was Organic Land Grid Array 603 (OLGA 603)
System Bus clock rate 400 MHz
SSE2 SIMD Extensions
Used in high-performance and mid-range dual processor enabled workstations
Xeon 2.0 GHz and up to 3.6 GHz
Introduced September 25, 2001

Itanium 2 (chronological entry)
Introduced July 2002
See main entry