32-bit processors: the Pentium ("I")

Pentium ("Classic")
Bus width 64 bits
System bus clock rate 60 or 66 MHz
Address bus 32 bits
Addressable Memory 4 GB
Virtual Memory 64 TB
Superscalar architecture brought 5X the performance of the 33 MHz 486DX processor
Runs on 5 volts
Used in desktops
16 KB of L1 cache
P5 - 0.8 µm process technology
Introduced March 22, 1993
Number of transistors 3.1 million
Socket 4 273 pin PGA processor package
Package dimensions 2.16" x 2.16"
Family 5 model 1
Variants
60 MHz with 100 MIPS (70.4 SPECint92, 55.1 SPECfp92 on Xpress 256 KB L2)
66 MHz with 112 MIPS (77.9 SPECint92, 63.6 SPECfp92 on Xpress 256 KB L2)
P54 - 0.6 µm process technology
Socket 7 296/321 pin PGA package
Number of transistors 3.2 million
Variants
75 MHz Introduced October 10, 1994
90 MHz Introduced March 7, 1994
100 MHz Introduced March 7, 1994
120 MHz Introduced March 27, 1995
P54C - 0.35 µm process technology
Number of transistors 3.3 million
90 mm² die size
Family 5 model 2
Variants
120 MHz Introduced March, 1995
133 MHz Introduced June, 1995
150 MHz Introduced January 4, 1996
166 MHz Introduced January 4, 1996
200 MHz Introduced June 10, 1996

80486DX4 (chronological entry)
Introduced March 7, 1994
See main entry

80386EX (Intel386 EX) (chronological entry)
Introduced August 1994
See main entry

Pentium Pro (chronological entry)
Introduced November 1995
See main entry
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Pentium with MMX Technology
P55C - 0.35 µm process technology
Introduced January 8, 1997
Intel MMX instructions
Socket 7 296/321 pin PGA (pin grid array) package
32 KB L1 cache
Number of transistors 4.5 million
System bus clock rate 66 MHz
Basic P55C is family 5 model 4, mobile are family 5 model 7 and 8
Variants
166 MHz Introduced January 8, 1997
200 MHz Introduced January 8, 1997
233 MHz Introduced June 2, 1997
166 MHz (Mobile) Introduced January 12, 1998
200 MHz (Mobile) Introduced September 8, 1997
233 MHz (Mobile) Introduced September 8, 1997
266 MHz (Mobile) Introduced January 12, 1998
300 MHz (Mobile) Introduced January 7, 1999
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32-bit processors: P6/Pentium M microarchitecture
[edit]
Pentium Pro
Introduced November 1, 1995
Precursor to Pentium II and III
Primarily used in server systems
Socket 8 processor package (387 pins) (Dual SPGA)
Number of transistors 5.5 million
Family 6 model 1
0.6 µm process technology
16 KB L1 cache
256 KB integrated L2 cache
60 MHz system bus clock rate
Variants
150 MHz
0.35 µm process technology, or 0.35 µm CPU with 0.6 µm L2 cache
Number of transistors 5.5 million
512 KB or 256 KB integrated L2 cache
60 or 66 MHz system bus clock rate
Variants
166 MHz (66 MHz bus clock rate, 512 KB 0.35 µm cache) Introduced November 1, 1995
180 MHz (60 MHz bus clock rate, 256 KB 0.6 µm cache) Introduced November 1, 1995
200 MHz (66 MHz bus clock rate, 256 KB 0.6 µm cache) Introduced November 1, 1995
200 MHz (66 MHz bus clock rate, 512 KB 0.35 µm cache) Introduced November 1, 1995
200 MHz (66 MHz bus clock rate, 1 MB 0.35 µm cache) Introduced August 18, 1997